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Thu, 14 Nov 2019 18:23:53 +0000 From: Omer Shpigelman To: "oded.gabbay@gmail.com" CC: "linux-kernel@vger.kernel.org" Subject: [PATCH 1/8] habanalabs: type specific MMU cache invalidation Thread-Topic: [PATCH 1/8] habanalabs: type specific MMU cache invalidation Thread-Index: AQHVmxirDVSYxw1jikyfisTruXA+CQ== Date: Thu, 14 Nov 2019 18:23:53 +0000 Message-ID: <20191114182346.22675-1-oshpigelman@habana.ai> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM0PR0402CA0007.eurprd04.prod.outlook.com (2603:10a6:208:15::20) To AM6PR0202MB3382.eurprd02.prod.outlook.com (2603:10a6:209:20::16) authentication-results: spf=none (sender IP is ) smtp.mailfrom=oshpigelman@habana.ai; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [31.154.190.6] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 90ef8ef3-cd5b-41e0-fec4-08d7692fcd82 x-ms-traffictypediagnostic: AM6PR0202MB3383: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6790; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: habana.ai X-MS-Exchange-CrossTenant-Network-Message-Id: 90ef8ef3-cd5b-41e0-fec4-08d7692fcd82 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Nov 2019 18:23:53.3225 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 0d4d4539-213c-4ed8-a251-dc9766ba127a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cIZcjAQSZJo3YoiBB0dskCj3qLKIXy1IpCSZJew+MmVf1CYQrazFH0wMeniCpUg/NgXoZjoNrfGU/asiO8BMAQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR0202MB3383 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the ability to invalidate the necessary MMU cache only. This ability is a prerequisite for future ASICs support. Note that in Goya ASIC, a single cache is used for both host/DRAM mapppings and hence this patch should not have any effect on current behaviour. Signed-off-by: Omer Shpigelman --- drivers/misc/habanalabs/goya/goya.c | 6 ++++-- drivers/misc/habanalabs/habanalabs.h | 11 ++++++----- drivers/misc/habanalabs/memory.c | 4 ++-- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/= goya/goya.c index 9712122d6cb1..3c22fb96a26f 100644 --- a/drivers/misc/habanalabs/goya/goya.c +++ b/drivers/misc/habanalabs/goya/goya.c @@ -2463,7 +2463,8 @@ int goya_mmu_init(struct hl_device *hdev) WREG32_AND(mmSTLB_STLB_FEATURE_EN, (~STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK)); =20 - hdev->asic_funcs->mmu_invalidate_cache(hdev, true); + hdev->asic_funcs->mmu_invalidate_cache(hdev, true, + VM_TYPE_USERPTR | VM_TYPE_PHYS_PACK); =20 WREG32(mmMMU_MMU_ENABLE, 1); WREG32(mmMMU_SPI_MASK, 0xF); @@ -4845,7 +4846,8 @@ static void goya_mmu_prepare(struct hl_device *hdev, = u32 asid) goya_mmu_prepare_reg(hdev, goya_mmu_regs[i], asid); } =20 -static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard= ) +static void goya_mmu_invalidate_cache(struct hl_device *hdev, bool is_hard= , + u32 flags) { struct goya_device *goya =3D hdev->asic_specific; u32 status, timeout_usec; diff --git a/drivers/misc/habanalabs/habanalabs.h b/drivers/misc/habanalabs= /habanalabs.h index 78aef59e690b..36d05c32f7ec 100644 --- a/drivers/misc/habanalabs/habanalabs.h +++ b/drivers/misc/habanalabs/habanalabs.h @@ -114,8 +114,8 @@ struct hw_queue_properties { * @VM_TYPE_PHYS_PACK: mapping of DRAM memory to device virtual address. */ enum vm_type_t { - VM_TYPE_USERPTR, - VM_TYPE_PHYS_PACK + VM_TYPE_USERPTR =3D 0x1, + VM_TYPE_PHYS_PACK =3D 0x2 }; =20 /** @@ -483,8 +483,8 @@ enum hl_pll_frequency { * @get_events_stat: retrieve event queue entries histogram. * @read_pte: read MMU page table entry from DRAM. * @write_pte: write MMU page table entry to DRAM. - * @mmu_invalidate_cache: flush MMU STLB cache, either with soft (L1 only)= or - * hard (L0 & L1) flush. + * @mmu_invalidate_cache: flush MMU STLB host/DRAM cache, either with soft + * (L1 only) or hard (L0 & L1) flush. * @mmu_invalidate_cache_range: flush specific MMU STLB cache lines with * ASID-VA-size mask. * @send_heartbeat: send is-alive packet to ArmCP and verify response. @@ -565,7 +565,8 @@ struct hl_asic_funcs { u32 *size); u64 (*read_pte)(struct hl_device *hdev, u64 addr); void (*write_pte)(struct hl_device *hdev, u64 addr, u64 val); - void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard); + void (*mmu_invalidate_cache)(struct hl_device *hdev, bool is_hard, + u32 flags); void (*mmu_invalidate_cache_range)(struct hl_device *hdev, bool is_hard, u32 asid, u64 va, u64 size); int (*send_heartbeat)(struct hl_device *hdev); diff --git a/drivers/misc/habanalabs/memory.c b/drivers/misc/habanalabs/mem= ory.c index 8ade9886a5a7..12db6609da27 100644 --- a/drivers/misc/habanalabs/memory.c +++ b/drivers/misc/habanalabs/memory.c @@ -944,7 +944,7 @@ static int map_device_va(struct hl_ctx *ctx, struct hl_= mem_in *args, goto map_err; } =20 - hdev->asic_funcs->mmu_invalidate_cache(hdev, false); + hdev->asic_funcs->mmu_invalidate_cache(hdev, false, *vm_type); =20 mutex_unlock(&ctx->mmu_lock); =20 @@ -1060,7 +1060,7 @@ static int unmap_device_va(struct hl_ctx *ctx, u64 va= ddr) =20 unmap_phys_pg_pack(ctx, vaddr, phys_pg_pack); =20 - hdev->asic_funcs->mmu_invalidate_cache(hdev, true); + hdev->asic_funcs->mmu_invalidate_cache(hdev, true, *vm_type); =20 mutex_unlock(&ctx->mmu_lock); =20 --=20 2.17.1