Received: by 2002:a25:7ec1:0:0:0:0:0 with SMTP id z184csp4615166ybc; Fri, 15 Nov 2019 07:25:20 -0800 (PST) X-Google-Smtp-Source: APXvYqwtKtver4wd6Q9TCuZkPS2Lzb3DHSsBOoVcPBnd9pDbXRiQ1IjLRACLYoj+EjeJa5YPMMEj X-Received: by 2002:a17:906:f209:: with SMTP id gt9mr1584910ejb.241.1573831520122; Fri, 15 Nov 2019 07:25:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1573831520; cv=none; d=google.com; s=arc-20160816; b=gp6UToQ27vmN7zk9UTj3Bn0h4B/uRjAD3R2RURPWKXQwToZKsK+Tc62irV/yCzNx3b d1030m2xZEtjqlcL6K0+FhoGuoOa8bjDpUCUEB866jHV88Lpw6Rb9q1xquakCCdZxdKv sL2p4tjlJlGTDYdbvDO+HIXyJMoQpCa39aNq+r5I740c3zL9KvOlayRJwGsiC7lBfqY5 wapEB4nhjQDGiYK+3AAphyj6+GEp5vjYY9KzsD2OPm71SyvrsNVMdcXZa1VDuBbIrYCO qj0vHDDecQTksXzFbjgrkEtA0Y4fZrzxrrLn2XcBox4uXDSBcliJAhx6sXG9kt0XW4kB qbHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-disposition:mime-version:references:message-id:subject:cc :to:from:date; bh=p2anmeM5euq5OLSw40v/gS7LVxy5Egs5GeXWLSnqrws=; b=do9UAVlsHxGLxj06eQTDCUa/zbtuAR4K28igvpE0t2BAfdxbYiDTPSCZFnVtamk5Y4 SMlW0laV+G8+ryR1TA7eTv8wrWLA3y7HsyUgrO2Pa5LaMVu8iyZoqMaCShkvKpYNFMMl PMcONu6KZZXLyFORan4FhrcHLdBF9eairQJripIC5fRnMPVCTs2cyZ5X4ZhgqpkTPcar QjFrncQjxOQqL//3UPabEtNPmPwbi+8uFa6VItLv4VDVarUW58FdgVe3IRalwNgAMI+/ Gx/xvOIruKWtWvVJisvPNwrOYbCWNUOmHE0+jbqSI3jes/7k8N+2mg4GnWqYAT6/Mqp3 VyXw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b10si6284599eds.63.2019.11.15.07.24.54; Fri, 15 Nov 2019 07:25:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727653AbfKOPUx (ORCPT + 99 others); Fri, 15 Nov 2019 10:20:53 -0500 Received: from foss.arm.com ([217.140.110.172]:60890 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727412AbfKOPUx (ORCPT ); Fri, 15 Nov 2019 10:20:53 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 67E7130E; Fri, 15 Nov 2019 07:20:52 -0800 (PST) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 18AF43F534; Fri, 15 Nov 2019 07:20:49 -0800 (PST) Date: Fri, 15 Nov 2019 15:20:48 +0000 From: Mark Rutland To: Sami Tolvanen Cc: Will Deacon , Catalin Marinas , Steven Rostedt , Masami Hiramatsu , Ard Biesheuvel , Dave Martin , Kees Cook , Laura Abbott , Marc Zyngier , Nick Desaulniers , Jann Horn , Miguel Ojeda , Masahiro Yamada , clang-built-linux@googlegroups.com, kernel-hardening@lists.openwall.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 14/14] arm64: implement Shadow Call Stack Message-ID: <20191115152047.GI41572@lakrids.cambridge.arm.com> References: <20191018161033.261971-1-samitolvanen@google.com> <20191105235608.107702-1-samitolvanen@google.com> <20191105235608.107702-15-samitolvanen@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191105235608.107702-15-samitolvanen@google.com> User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 05, 2019 at 03:56:08PM -0800, Sami Tolvanen wrote: > This change implements shadow stack switching, initial SCS set-up, > and interrupt shadow stacks for arm64. Each CPU also has an overflow stack, and two SDEI stacks, which should presumably be given their own SCS. SDEI is effectively a software-NMI, so it should almost certainly have the same treatement as IRQ. > +static __always_inline void scs_save(struct task_struct *tsk) > +{ > + void *s; > + > + asm volatile("mov %0, x18" : "=r" (s)); > + task_set_scs(tsk, s); > +} An alternative would be to follow , and have: register unsigned long *current_scs_pointer asm ("x18"); static __always_inline void scs_save(struct task_struct *tsk) { task_set_scs(tsk, current_scs_pointer); } ... which would avoid the need for a temporary register where this is used. However, given we only use this in cpu_die(), having this as-is should be fine. Maybe the asm volatile is preferable if we use this elsewhere, so that we know we have a consistent snapshot that the compiler can't reload, etc. [...] > @@ -409,6 +428,10 @@ alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 > */ > .macro irq_stack_exit > mov sp, x19 > +#ifdef CONFIG_SHADOW_CALL_STACK > + /* x20 is also preserved */ > + mov x18, x20 > +#endif > .endm Can we please fold this comment into the one above, and have: /* * The callee-saved regs (x19-x29) should be preserved between * irq_stack_entry and irq_stack_exit. */ .macro irq_stack_exit mov sp, x19 #ifdef CONFIG_SHADOW_CALL_STACK mov x18, x20 #endif .endm Thanks, Mark.