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Subject: Re: [PATCH] perf/x86/intel: Avoid PEBS_ENABLE MSR access in PMI
From:   "Liang, Kan" <kan.liang@linux.intel.com>
To:     Peter Zijlstra <peterz@infradead.org>
Cc:     acme@redhat.com, mingo@kernel.org, linux-kernel@vger.kernel.org,
        ak@linux.intel.com, eranian@google.com
References: <20191115133917.24424-1-kan.liang@linux.intel.com>
 <20191115140739.GM4131@hirez.programming.kicks-ass.net>
 <c0f562aa-39f3-1291-edd7-17c46178d1e3@linux.intel.com>
Message-ID: <3e117702-c07f-bd58-9931-766c2698b5d7@linux.intel.com>
Date:   Fri, 15 Nov 2019 13:04:50 -0500
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On 11/15/2019 9:46 AM, Liang, Kan wrote:
> 
> 
> On 11/15/2019 9:07 AM, Peter Zijlstra wrote:
>> On Fri, Nov 15, 2019 at 05:39:17AM -0800, kan.liang@linux.intel.com 
>> wrote:
>>> From: Kan Liang <kan.liang@linux.intel.com>
>>>
>>> The perf PMI handler, intel_pmu_handle_irq(), currently does
>>> unnecessary MSR accesses when PEBS is enabled.
>>>
>>> When entering the handler, global ctrl is explicitly disabled. All
>>> counters do not count anymore. It doesn't matter if the PEBS is
>>> enabled or disabled. Furthermore, cpuc->pebs_enabled is not changed
>>> in PMI. The PEBS status doesn't change. The PEBS_ENABLE MSR doesn't need
>>> to be changed either.
>>
>> PMI can throttle, and iirc x86_pmu_stop() ends up in
>> intel_pmu_pebs_disable()
>>
> 
> Right, the declaration is inaccurate. I will fix it in v2.
> But the patch still works for the case of PMI throttle.
> The intel_pmu_pebs_disable() will update cpuc->pebs_enabled and 
> unconditionally modify MSR_IA32_PEBS_ENABLE.

It seems not true for a corner case.
PMI may land after cpuc->enabled=0 in x86_pmu_disable() and PMI throttle 
may be triggered for the PMI. For this rare case, 
intel_pmu_pebs_disable() will not touch MSR_IA32_PEBS_ENABLE.

I don't have a test case for this rare corner case. But I think we may 
have to handle it in PMI handler as well. I will add the codes as below 
to V2.

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index bc6468329c52..7198a372a5ab 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2620,6 +2624,15 @@ static int handle_pmi_common(struct pt_regs 
*regs, u64 status)
                 handled++;
                 x86_pmu.drain_pebs(regs);
                 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
+
+               /*
+                * PMI may land after cpuc->enabled=0 in 
x86_pmu_disable() and
+                * PMI throttle may be triggered for the PMI.
+                * For this rare case, intel_pmu_pebs_disable() will not 
touch
+                * MSR_IA32_PEBS_ENABLE. Explicitly disable the PEBS here.
+                */
+               if (unlikely(!cpuc->enabled && !cpuc->pebs_enabled))
+                       wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
         }


Thanks,
Kan

> When exiting the handler, current perf re-write the PEBS MSR according 
> to the updated cpuc->pebs_enabled, which is still unnecessary.
>