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[70.163.223.149]) by smtp.gmail.com with ESMTPSA id q34sm10731806pjb.15.2019.11.15.11.14.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Nov 2019 11:14:50 -0800 (PST) Date: Fri, 15 Nov 2019 12:14:49 -0700 From: Jerry Snitselaar To: Jarkko Sakkinen Cc: Stefan Berger , linux-integrity@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: question about setting TPM_CHIP_FLAG_IRQ in tpm_tis_core_init Message-ID: <20191115191449.qnqgos4nli3tjsdw@cantor> Reply-To: Jerry Snitselaar Mail-Followup-To: Jarkko Sakkinen , Stefan Berger , linux-integrity@vger.kernel.org, linux-kernel@vger.kernel.org References: <20191112033637.kxotlhm6mtr5irvd@cantor> <6d6f0899-8ba0-d6cf-ef3b-317ca698b687@linux.ibm.com> <20191112201716.GA12340@linux.intel.com> MIME-Version: 1.0 In-Reply-To: <20191112201716.GA12340@linux.intel.com> X-MC-Unique: GQGJvN8hPmeaSBndARBd6w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue Nov 12 19, Jarkko Sakkinen wrote: >On Tue, Nov 12, 2019 at 08:28:57AM -0500, Stefan Berger wrote: >> I set this flag for the TIS because it wasn't set anywhere else. >> tpm_tis_send() wouldn't set the flag but go via the path: >> >> if (!(chip->flags & TPM_CHIP_FLAG_IRQ) || priv->irq_tested) >> >> =A0=A0=A0=A0=A0=A0=A0 return tpm_tis_send_main(chip, buf, len); > >Wondering why this isn't just "if (priv->irq_tested)"? Isn't that the >whole point. The tail is the test part e.g. should be executed when >IRQ testing is done. > >/Jarkko > I wonder if it would make sense to rename tpm_tis_send_main to tpm_tis_send= , move the irq testing bits from the current tpm_tis_send to tpm_tis_gen_inte= rrupt, and have tpm_tis_gen_interrupt build its own tpmbufs to send via tpm_tis_se= nd for the testing. Have all the irq testing bits are off on their own and sep= arated out from sending commands.