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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id x12sm14425032pfm.130.2019.11.16.08.51.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Nov 2019 08:51:52 -0800 (PST) Date: Sat, 16 Nov 2019 08:51:50 -0800 From: Bjorn Andersson To: Brian Masney Cc: sboyd@kernel.org, mturquette@baylibre.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, jonathan@marek.ca Subject: Re: [PATCH] clk: qcom: mmcc8974: move gfx3d_clk_src from the mmcc to rpm Message-ID: <20191116165150.GB25371@yoga> References: <20191115123931.18919-1-masneyb@onstation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191115123931.18919-1-masneyb@onstation.org> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri 15 Nov 04:39 PST 2019, Brian Masney wrote: > gfx3d_clk_src for msm8974 was introduced into the MMCC by > commit d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia > clock controller (MMCC)") to ensure that all of the clocks for > this platform are documented upstream. This clock actually belongs > on the RPM. Since then, commit 685dc94b7d8f ("clk: qcom: smd-rpmcc: > Add msm8974 clocks") was introduced, which contains the proper > definition for gfx3d_clk_src. Let's drop the definition from the > mmcc and register the clock with the rpm instead. > > This change was tested on a Nexus 5 (hammerhead) phone. > > Signed-off-by: Brian Masney Reviewed-by: Bjorn Andersson > --- > drivers/clk/qcom/clk-smd-rpm.c | 2 ++ > drivers/clk/qcom/mmcc-msm8974.c | 13 ------------- > 2 files changed, 2 insertions(+), 13 deletions(-) > > diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c > index 60aae7543608..2db31dbe47e9 100644 > --- a/drivers/clk/qcom/clk-smd-rpm.c > +++ b/drivers/clk/qcom/clk-smd-rpm.c > @@ -486,6 +486,8 @@ static struct clk_smd_rpm *msm8974_clks[] = { > [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, > [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, > [RPM_SMD_BIMC_CLK] = &msm8974_bimc_clk, > + [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, > + [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, > [RPM_SMD_BIMC_A_CLK] = &msm8974_bimc_a_clk, > [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, > [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, > diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c > index bcb0a397ef91..015426262d08 100644 > --- a/drivers/clk/qcom/mmcc-msm8974.c > +++ b/drivers/clk/qcom/mmcc-msm8974.c > @@ -452,18 +452,6 @@ static struct clk_rcg2 mdp_clk_src = { > }, > }; > > -static struct clk_rcg2 gfx3d_clk_src = { > - .cmd_rcgr = 0x4000, > - .hid_width = 5, > - .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map, > - .clkr.hw.init = &(struct clk_init_data){ > - .name = "gfx3d_clk_src", > - .parent_names = mmcc_xo_mmpll0_1_2_gpll0, > - .num_parents = 5, > - .ops = &clk_rcg2_ops, > - }, > -}; > - > static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = { > F(75000000, P_GPLL0, 8, 0, 0), > F(133330000, P_GPLL0, 4.5, 0, 0), > @@ -2411,7 +2399,6 @@ static struct clk_regmap *mmcc_msm8974_clocks[] = { > [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, > [VFE1_CLK_SRC] = &vfe1_clk_src.clkr, > [MDP_CLK_SRC] = &mdp_clk_src.clkr, > - [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, > [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr, > [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr, > [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr, > -- > 2.21.0 >