Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Peng Fan <peng.fan@nxp.com>, "sboyd@kernel.org" <sboyd@kernel.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>
CC:     "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        Abel Vesa <abel.vesa@nxp.com>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Anson Huang <anson.huang@nxp.com>,
        Jacky Bai <ping.bai@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V2 2/4] clk: imx: imx8mn: Switch to clk_hw based API
Thread-Topic: [PATCH V2 2/4] clk: imx: imx8mn: Switch to clk_hw based API
Thread-Index: AQHVktMr9vdJ3yj43k2cixXCwuTSvQ==
Date:   Mon, 18 Nov 2019 13:06:26 +0000
Message-ID: <VI1PR04MB7023CC47DC123A66627940E9EE4D0@VI1PR04MB7023.eurprd04.prod.outlook.com>
References: <1572846270-24375-1-git-send-email-peng.fan@nxp.com>
 <1572846270-24375-3-git-send-email-peng.fan@nxp.com>
Accept-Language: en-US
Content-Language: en-US
received-spf: None (protection.outlook.com: nxp.com does not designate
 permitted sender hosts)
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 627280d4-78d6-4979-99c9-08d76c281e98
X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Nov 2019 13:06:26.2271
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: YIcpygG943t6Lbkw3x4HE92SPTJToxdzQDq5xJl7Q9T3DGvv5G3Xdqa/rqJgNqS/wQ8EIcVEjQ9IIB68zkMrpg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4846
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 2019-11-04 7:46 AM, Peng Fan wrote:=0A=
> From: Peng Fan <peng.fan@nxp.com>=0A=
> =0A=
> Switch the entire clk-imx8mn driver to clk_hw based API.=0A=
> This allows us to move closer to a clear split between=0A=
> consumer and provider clk APIs.=0A=
=0A=
> -	clks[IMX8MN_AUDIO_PLL1] =3D imx_clk_pll14xx("audio_pll1", "audio_pll1_r=
ef_sel", base, &imx_1443x_pll);=0A=
> -	clks[IMX8MN_AUDIO_PLL2] =3D imx_clk_pll14xx("audio_pll2", "audio_pll2_r=
ef_sel", base + 0x14, &imx_1443x_pll);=0A=
> -	clks[IMX8MN_VIDEO_PLL1] =3D imx_clk_pll14xx("video_pll1", "video_pll1_r=
ef_sel", base + 0x28, &imx_1443x_pll);=0A=
> -	clks[IMX8MN_DRAM_PLL] =3D imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel=
", base + 0x50, &imx_1443x_pll);=0A=
> -	clks[IMX8MN_GPU_PLL] =3D imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", =
base + 0x64, &imx_1416x_pll);=0A=
> -	clks[IMX8MN_VPU_PLL] =3D imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", =
base + 0x74, &imx_1416x_pll);=0A=
> -	clks[IMX8MN_ARM_PLL] =3D imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", =
base + 0x84, &imx_1416x_pll);=0A=
> -	clks[IMX8MN_SYS_PLL1] =3D imx_clk_fixed("sys_pll1", 800000000);=0A=
> -	clks[IMX8MN_SYS_PLL2] =3D imx_clk_fixed("sys_pll2", 1000000000);=0A=
> -	clks[IMX8MN_SYS_PLL3] =3D imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel=
", base + 0x114, &imx_1416x_pll);=0A=
> +	clks[IMX8MN_AUDIO_PLL1] =3D imx_clk_hw_pll14xx("audio_pll1", "audio_pll=
1_ref_sel", base, &imx_1416x_pll);=0A=
> +	clks[IMX8MN_AUDIO_PLL2] =3D imx_clk_hw_pll14xx("audio_pll2", "audio_pll=
2_ref_sel", base + 0x14, &imx_1416x_pll);=0A=
> +	clks[IMX8MN_VIDEO_PLL1] =3D imx_clk_hw_pll14xx("video_pll1", "video_pll=
1_ref_sel", base + 0x28, &imx_1416x_pll);=0A=
> +	clks[IMX8MN_DRAM_PLL] =3D imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_=
sel", base + 0x50, &imx_1416x_pll);=0A=
> +	clks[IMX8MN_GPU_PLL] =3D imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel=
", base + 0x64, &imx_1416x_pll);=0A=
> +	clks[IMX8MN_VPU_PLL] =3D imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel=
", base + 0x74, &imx_1416x_pll);=0A=
> +	clks[IMX8MN_ARM_PLL] =3D imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel=
", base + 0x84, &imx_1416x_pll);=0A=
> +	clks[IMX8MN_SYS_PLL1] =3D imx_clk_hw_fixed("sys_pll1", 800000000);=0A=
> +	clks[IMX8MN_SYS_PLL2] =3D imx_clk_hw_fixed("sys_pll2", 1000000000);=0A=
> +	clks[IMX8MN_SYS_PLL3] =3D imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_=
sel", base + 0x114, &imx_1416x_pll);=0A=
=0A=
You are switching audio/video/dram PLL from imx_1443x_pll to =0A=
imx_1416x_pll, are you sure this is correct?=0A=
=0A=
If this is intentional it should be an separate patch.=0A=
=0A=
> -	clks[IMX8MN_CLK_ARM] =3D imx_clk_cpu("arm", "arm_a53_div",=0A=
> -					   clks[IMX8MN_CLK_A53_DIV],=0A=
> -					   clks[IMX8MN_CLK_A53_SRC],=0A=
> -					   clks[IMX8MN_ARM_PLL_OUT],=0A=
> -					   clks[IMX8MN_CLK_24M]);=0A=
=0A=
> +	clks[IMX8MN_CLK_ARM] =3D imx_clk_hw_cpu("arm", "arm_a53_div",=0A=
> +					      clks[IMX8MN_CLK_A53_DIV]->clk,=0A=
> +					      clks[IMX8MN_CLK_A53_SRC]->clk,=0A=
> +					      clks[IMX8MN_ARM_PLL_OUT]->clk,=0A=
> +					      clks[IMX8MN_CLK_24M]->clk);=0A=
=0A=
This series seems to be against Shawn's clk/imx but there is an =0A=
additional patch in Stephen's tree which changes this 24M to PLL1_800M. =0A=
Maybe that should be pulled into clk/imx? Otherwise it might spawn an =0A=
unreadable merge conflicts since almost the entire file is rewritten.=0A=
=0A=
--=0A=
Regards,=0A=
Leonard=0A=