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Date: Sat, 13 Oct 2001 16:27:30 +0200 (CEST)
From: Dave Jones <davej@suse.de>
To: Mikael Pettersson <mikpe@csd.uu.se>
Cc: <alan@lxorguk.ukuu.org.uk>, <linux-kernel@vger.kernel.org>,
        <torvalds@transmeta.com>
Subject: Re: [PATCH] Pentium IV cacheline size.
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On Sat, 13 Oct 2001, Mikael Pettersson wrote:

> According to the P4 and Xeon optimisation manual (#248966-03), the
> L1 cache has a 64-byte line size and the L2 cache has a 128-byte
> line size. (Page 1-18, Table 1-1.) Perhaps someone just confused

Great, conflicting documentation.
#24547203 (Vol3 : System programming guide) has this to say..
(page 325)
"The cache lines for the L1 and L2 caches in the Pentium 4 processor
 are 64 bytes wide"


regards,

Dave.

-- 
| Dave Jones.        http://www.codemonkey.org.uk
| SuSE Labs

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