Received: by 2002:a25:7ec1:0:0:0:0:0 with SMTP id z184csp140849ybc; Mon, 18 Nov 2019 22:03:41 -0800 (PST) X-Google-Smtp-Source: APXvYqy53nHyohnzxdheIZ+Vuu5BE+o6QdF5+JWKJAhiZ5mt34osDVbkhLXAtNGjfJBEQf9iVJzg X-Received: by 2002:a17:906:1c07:: with SMTP id k7mr31497496ejg.229.1574143421032; Mon, 18 Nov 2019 22:03:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574143421; cv=none; d=google.com; s=arc-20160816; b=Oh9DMQyNBFkidRbj3VoIPHwMN/YW7w7HvKN/aLmiRRE3d7k1hHy5IwiXwk68WZHfQP MC6C8M81qt/Hv9LCxDeWMkpFoTmJyyEYmT0zmLnZczIkVsKEwENJqPQrB0JwOAnJl4rJ cHZVLDDPPHx4d+M33X3nOCTlfH/XPUfdfKSSUCiZ7ue+EyeRZNCZ5ic+EAujsFyCv9r7 3bcggQ/soorlm+/vAuqlXaYvYvg9GqtpfvUMGyvfUiOMhSx1DhW8FofPDw4UfYKA5nOj zc9HlJYSVBJIy+hA9tAsLUnHNBQiFK/ua2MiB4GIUn8AZJ9RxNnQAnyULfgmMSKBcG6i C9DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BYAGRo32fz1JPPFQKQEi1D9dqoRfMB0q7ZtuHZPOKac=; b=TNOg6XQRfTvinPbqNnYTHDRvJU3BUyInVZxOcFkaJXOQKBrmhrkG0H0NIMBEMWCpC5 Ww6sG8Ql53oiQ+GrUeLB12OPMUah9xfHSOmNMff9Umj7wll9u04UAZJjTag77/q/Qe9W tiektC27irCRxQjmR0LvnIy8JEhKRS2LpQND0YPyMKXcvscnFDGvXEfx0KfSrtRrMJMP bXl1lMamR66QUw5XcoBHQTQJp/mrvIrUlgbaOO1YccLRdm9IwvkYM37p00XeIrv2MRu7 ScIRKWjFVUzux1Gm3pQ8S1Vgr/3LwfbjU2BPuEkf3PqwVXmMC5DJDkQ51M51RlcyX49b Lpmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=mCJacPez; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u25si10199358edt.225.2019.11.18.22.03.16; Mon, 18 Nov 2019 22:03:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=mCJacPez; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731115AbfKSFqc (ORCPT + 99 others); Tue, 19 Nov 2019 00:46:32 -0500 Received: from mail.kernel.org ([198.145.29.99]:42604 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730837AbfKSFq3 (ORCPT ); Tue, 19 Nov 2019 00:46:29 -0500 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id D917B2071B; Tue, 19 Nov 2019 05:46:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1574142388; bh=wa7YDgehiZ0AGsCxw7mUn8MD6uR/Hfws7/JZg4+w6Mg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mCJacPezY2BLytjf0SLHRY8ehkaJ6Tf++ts7yCInZH4EFYISBqaL5Viu8YlxDlx4J Jc/6HQlSVCc0VQpU6w6w9+ViZn5gnbDp+MSSG/+wBq6P1kA2vsPw2kwzxL52K2tPuF xTSO/K8QQt9ivb0dJSmFJ7KT9e8UNh1UlYlTStiQ= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Martin Blumenstingl , Neil Armstrong , Kevin Hilman , Sasha Levin Subject: [PATCH 4.14 064/239] ARM: dts: meson8: fix the clock controller register size Date: Tue, 19 Nov 2019 06:17:44 +0100 Message-Id: <20191119051311.680220020@linuxfoundation.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191119051255.850204959@linuxfoundation.org> References: <20191119051255.850204959@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Martin Blumenstingl [ Upstream commit f7f9da89bc4f61e33f7b9f5c75c4efdc1f0455d8 ] The clock controller registers are not 0x460 wide because the reset controller starts at CBUS 0x4404. This currently overlaps with the clock controller (which is at CBUS 0x4000). There is no public documentation available on the actual size of the clock controller's register area (also called "HHI"). However, in Amlogic's GPL kernel sources the last "HHI" register is HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size doesn't seem unlikely. Fixes: 2c323c43a3d619 ("ARM: dts: meson8: add and use the real clock controller") Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Signed-off-by: Sasha Levin --- arch/arm/boot/dts/meson8.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index b98d44fde6b60..e3ae85d65b39b 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -170,7 +170,7 @@ #clock-cells = <1>; #reset-cells = <1>; compatible = "amlogic,meson8-clkc"; - reg = <0x8000 0x4>, <0x4000 0x460>; + reg = <0x8000 0x4>, <0x4000 0x400>; }; pwm_ef: pwm@86c0 { -- 2.20.1