Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Abel Vesa <abel.vesa@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
        Stephen Boyd <sboyd@kernel.org>
CC:     Aisheng Dong <aisheng.dong@nxp.com>,
        Sascha Hauer <kernel@pengutronix.de>,
        Jacky Bai <ping.bai@nxp.com>, Peng Fan <peng.fan@nxp.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 5/9] clk: imx: Rename sccg and frac pll register to
 suggest clk_hw
Thread-Topic: [PATCH 5/9] clk: imx: Rename sccg and frac pll register to
 suggest clk_hw
Thread-Index: AQHVnuLaLySjs9P8E0eseKYJ9/xfoA==
Date:   Tue, 19 Nov 2019 16:32:27 +0000
Message-ID: <VI1PR04MB702360DD60D297B19F346B7FEE4C0@VI1PR04MB7023.eurprd04.prod.outlook.com>
References: <1574172496-12987-1-git-send-email-abel.vesa@nxp.com>
 <1574172496-12987-6-git-send-email-abel.vesa@nxp.com>
Accept-Language: en-US
Content-Language: en-US
received-spf: None (protection.outlook.com: nxp.com does not designate
 permitted sender hosts)
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 797010f2-4026-4d44-6531-08d76d0e10eb
X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Nov 2019 16:32:27.5961
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: JqSLlQ6l68t3C/gD99wBcRL8sjAFsCXLvtdUEEeG+2bv/DG32A8k+6CSDMkRE/x4yVANh3BVdD98ezN2oDyitQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB4351
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 2019-11-19 4:08 PM, Abel Vesa wrote:=0A=
> Renaming the imx_clk_frac_pll and imx_clk_sccg_pll register functions to=
=0A=
> imx_clk_hw_frac_pll, respectively imx_clk_hw_sccg_pll to be more obvious=
=0A=
> that they are clk_hw based=0A=
On a somewake unrelated note there is no "SCCG", reference manual refers =
=0A=
to this as "SSCG": "Spread Sprectum Clock Generator"=0A=
=0A=
These wrapping macros don't correctly forward null or error either.=0A=
=0A=
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>=0A=
> ---=0A=
>   drivers/clk/imx/clk-frac-pll.c |  7 ++++---=0A=
>   drivers/clk/imx/clk-sccg-pll.c |  4 ++--=0A=
>   drivers/clk/imx/clk.h          | 12 ++++++++++--=0A=
>   3 files changed, 16 insertions(+), 7 deletions(-)=0A=
> =0A=
> diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pl=
l.c=0A=
> index fece503..101e0a3 100644=0A=
> --- a/drivers/clk/imx/clk-frac-pll.c=0A=
> +++ b/drivers/clk/imx/clk-frac-pll.c=0A=
> @@ -201,8 +201,9 @@ static const struct clk_ops clk_frac_pll_ops =3D {=0A=
>   	.set_rate	=3D clk_pll_set_rate,=0A=
>   };=0A=
>   =0A=
> -struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,=
=0A=
> -			     void __iomem *base)=0A=
> +struct clk_hw *imx_clk_hw_frac_pll(const char *name,=0A=
> +				   const char *parent_name,=0A=
> +				   void __iomem *base)=0A=
>   {=0A=
>   	struct clk_init_data init;=0A=
>   	struct clk_frac_pll *pll;=0A=
> @@ -230,5 +231,5 @@ struct clk *imx_clk_frac_pll(const char *name, const =
char *parent_name,=0A=
>   		return ERR_PTR(ret);=0A=
>   	}=0A=
>   =0A=
> -	return hw->clk;=0A=
> +	return hw;=0A=
>   }=0A=
> diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pl=
l.c=0A=
> index 5d65f65..2cf8748 100644=0A=
> --- a/drivers/clk/imx/clk-sccg-pll.c=0A=
> +++ b/drivers/clk/imx/clk-sccg-pll.c=0A=
> @@ -506,7 +506,7 @@ static const struct clk_ops clk_sccg_pll_ops =3D {=0A=
>   	.determine_rate	=3D clk_sccg_pll_determine_rate,=0A=
>   };=0A=
>   =0A=
> -struct clk *imx_clk_sccg_pll(const char *name,=0A=
> +struct clk_hw *imx_clk_hw_sccg_pll(const char *name,=0A=
>   				const char * const *parent_names,=0A=
>   				u8 num_parents,=0A=
>   				u8 parent, u8 bypass1, u8 bypass2,=0A=
> @@ -545,5 +545,5 @@ struct clk *imx_clk_sccg_pll(const char *name,=0A=
>   		return ERR_PTR(ret);=0A=
>   	}=0A=
>   =0A=
> -	return hw->clk;=0A=
> +	return hw;=0A=
>   }=0A=
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h=0A=
> index 71b21ab..15c6f54 100644=0A=
> --- a/drivers/clk/imx/clk.h=0A=
> +++ b/drivers/clk/imx/clk.h=0A=
> @@ -115,6 +115,14 @@ extern struct imx_pll14xx_clk imx_1443x_pll;=0A=
>   #define imx_clk_pllv2(name, parent, base) \=0A=
>   	imx_clk_hw_pllv2(name, parent, base)->clk=0A=
>   =0A=
> +#define imx_clk_frac_pll(name, parent_name, base) \=0A=
> +	imx_clk_hw_frac_pll(name, parent_name, base)->clk=0A=
> +=0A=
> +#define imx_clk_sccg_pll(name, parent_names, num_parents, parent,\=0A=
> +				bypass1, bypass2, base, flags) \=0A=
> +	imx_clk_hw_sccg_pll(name, parent_names, num_parents, parent,\=0A=
> +				bypass1, bypass2, base, flags)->clk \=0A=
> +=0A=
>   struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,=
=0A=
>   		 void __iomem *base, const struct imx_pll14xx_clk *pll_clk);=0A=
>   =0A=
> @@ -124,10 +132,10 @@ struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type=
 type, const char *name,=0A=
>   struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,=
=0A=
>   		void __iomem *base);=0A=
>   =0A=
> -struct clk *imx_clk_frac_pll(const char *name, const char *parent_name,=
=0A=
> +struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_=
name,=0A=
>   			     void __iomem *base);=0A=
>   =0A=
> -struct clk *imx_clk_sccg_pll(const char *name,=0A=
> +struct clk_hw *imx_clk_hw_sccg_pll(const char *name,=0A=
>   				const char * const *parent_names,=0A=
>   				u8 num_parents,=0A=
>   				u8 parent, u8 bypass1, u8 bypass2,=0A=
> =0A=
=0A=