Received: by 2002:a25:7ec1:0:0:0:0:0 with SMTP id z184csp929667ybc; Tue, 19 Nov 2019 11:34:36 -0800 (PST) X-Google-Smtp-Source: APXvYqykVSiSSK2xm/OyZ6veEb60gDD7HngGrVaIZZLApfEXsNCDVECJkgiQ7EQfx3N9lNdaa374 X-Received: by 2002:a17:906:95c4:: with SMTP id n4mr36634832ejy.39.1574192076640; Tue, 19 Nov 2019 11:34:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574192076; cv=none; d=google.com; s=arc-20160816; b=GoDhTaCm9E7UNkBlf0zmO6MAdFkGAKecYHC61y0Pesw8LGrDb7HDrGbZZw7528pvmZ rA/M7PQOW9o770NgO23RdEReErFD55xCLGau1UwLeS1FzIxXWPJTQUTgmKGWTRPcs0M/ h+nm8ufcYhyrCroEHcPuK8Yu6SNexGp1eiIqVRdGoLKzWHfSOrgevjoB6VRiKco2X8q9 U0OP8phPeJi1m6KH/ikSB5VACGL/zVqC6T+4aK1ajgNBMsqmpQjKBu4Nu1ghbbCKVCH0 73nGXecYlpcVxz1dqtsaXrQhCVgBSOxy7qxCUf+pEThFWZ/l8rBbjgsNL94zF5RA9slv eDYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject:dkim-signature; bh=f4Ums0924t9zSVHk8HQR4M4Yx48zZgYQim0som1QWS8=; b=m8xynjzdPioh3U8xiokzoQTChtg23FDo8xsrP6sNaRiF6euMiu22Fazx3qkJHUAUSO 0N+vq+z4SVluCjG5MR4gIg7wvlnM9/4vscj5q09Nw+yg+PiNBQnoVAeFu7g5HMHZWgLD sdczdX997fs0kfHD+qnqCq7BQ2cpzoUaA79kDYuY9uJlnLGW+b1TMAjS0U4DSGIQXSt/ fqqcr3twO6arEmTNh2WVXPWYNBEzX4TFFj40DrpRkxbSXFRvB9G5YK4eO2c4vVA66F8K zCREA8fh+8YzDgwteFxdC+Ro4bj6nFqzZXMYX7/0MRrG36DpaBXA9w167ST9Tg1N5ybz jPCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=VSqDPN14; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t17si5765184eji.394.2019.11.19.11.34.12; Tue, 19 Nov 2019 11:34:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=VSqDPN14; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727549AbfKSTc3 (ORCPT + 99 others); Tue, 19 Nov 2019 14:32:29 -0500 Received: from mail-lf1-f68.google.com ([209.85.167.68]:43433 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726892AbfKSTc3 (ORCPT ); Tue, 19 Nov 2019 14:32:29 -0500 Received: by mail-lf1-f68.google.com with SMTP id l14so11405148lfh.10; Tue, 19 Nov 2019 11:32:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=f4Ums0924t9zSVHk8HQR4M4Yx48zZgYQim0som1QWS8=; b=VSqDPN14Uxd1TYS6NPANOwoC8V3gSO806r2757G40dkotN35IBvBt2Afxrl1XAZ8nm EYlHXhdL+s4jRTB6Qj8us59XdjQlzdeOi+UicUhgdqUL+J6lvNZEAB7NyJHHTGZrsI6w GBHoyVC/gFnW/QCiRuQ05y6rrSQuhXyfBFXOVNqlj8CsSkkReZXj46VEdcNmYkCRekpM PnO9uDtNO9FtTHfuXPWt6u+wzdv/O0U2MxaQHpmFLmJavbR+Y396XOSKWYtAg5ii9RLN JWH97ctoHItfnClYhDIPNGyGo4C74LyA2bwj4SD4Nk8s2kgTmTqJUUBd6XlwANo9FIA7 rihg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=f4Ums0924t9zSVHk8HQR4M4Yx48zZgYQim0som1QWS8=; b=dBJdK7gpz+r+R9XXpBmIdNbmfCCelhe7H6SvzSZgk3FvLd/LHrOrmL5IGQ8eIYQ+ab QcSuPTxHxJXYs0t+lM3UEWkPXs61pYhsuoeIzv4G147mpD0D/NiSSJpxeEW2W9S/jWqo OLNwa72ySrY/SldJW8gNlNIyrLJDYzO85zYOuDgTmm0eOUwYf1HagzrkLWrOFEoLSh6+ cKDXmuSEqHBNglpbyUB4cGHRRHeEH+7Isnd3m9I3xnfb9Xif5oLkLoxRaGSwrQSnYa2u vgHPfWtnrsviAWEqWwiaeNNfehXAg9mejOXK1Kf/OphV5SzfvZS/d4mTgSQpZFgifKOv dLmQ== X-Gm-Message-State: APjAAAWdoA2NJ0LyDAAzZ2GSgbPopl0QG7yH1/UDtz6ylYkt/C4WffOA Qc1rtZ5jVrkKaLiqrHpX1dhTS1tg X-Received: by 2002:a19:22c4:: with SMTP id i187mr5060364lfi.152.1574191945277; Tue, 19 Nov 2019 11:32:25 -0800 (PST) Received: from [192.168.2.145] (79-139-233-37.dynamic.spd-mgts.ru. [79.139.233.37]) by smtp.googlemail.com with ESMTPSA id w26sm7078376lfl.37.2019.11.19.11.32.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Nov 2019 11:32:24 -0800 (PST) Subject: Re: [PATCH v1 01/17] soc: tegra: pmc: Add helper functions for PLLM overrides To: Sowjanya Komatineni , thierry.reding@gmail.com, jonathanh@nvidia.com, mperttunen@nvidia.com, gregkh@linuxfoundation.org, sboyd@kernel.org, tglx@linutronix.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: allison@lohutok.net, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mturquette@baylibre.com, horms+renesas@verge.net.au, Jisheng.Zhang@synaptics.com, krzk@kernel.org, arnd@arndb.de, spujar@nvidia.com, josephl@nvidia.com, vidyas@nvidia.com, daniel.lezcano@linaro.org, mmaddireddy@nvidia.com, markz@nvidia.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <1574146234-3871-1-git-send-email-skomatineni@nvidia.com> <1574146234-3871-2-git-send-email-skomatineni@nvidia.com> From: Dmitry Osipenko Message-ID: Date: Tue, 19 Nov 2019 22:32:22 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <1574146234-3871-2-git-send-email-skomatineni@nvidia.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 19.11.2019 09:50, Sowjanya Komatineni пишет: > Tegra PMC has an option to override the CAR PLLM configuration during > the warmboot. > > PLLM dividers and enable overrides from Tegra PMC are applicable only > when PLLM_OVERRIDE bit in PMC_PLLP_WB0_OVERRIDE register is set by Tegra > the bootloader. During warmboot based on this override enable, PLLM > divider and enable configuration from overrides in PMC or from CAR > module are used. > > Currently PLLM overrides in Tegra PMC are directly programmed by the Tegra > clock driver and with this when PMC is in secure mode, any direct PMC > register access from non-secure world will not go through. > > This patch adds helper functions for use by the Tegra clock driver to > configure these PLLM overrides during PLLM clock rate and state changes. > > Signed-off-by: Sowjanya Komatineni > --- > drivers/soc/tegra/pmc.c | 204 +++++++++++++++++++++++++++++++++++++++++++++++- > include/soc/tegra/pmc.h | 5 ++ > 2 files changed, 205 insertions(+), 4 deletions(-) > > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c > index 8db63cfba833..224e7cf8dc00 100644 > --- a/drivers/soc/tegra/pmc.c > +++ b/drivers/soc/tegra/pmc.c > @@ -79,6 +79,14 @@ > > #define PMC_PWR_DET 0x48 > > +#define TEGRA186_PMC_PLLP_WB0_OVERRIDE 0x4c > +#define PMC_PLLP_WB0_OVERRIDE 0xf8 > +#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) > +#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE BIT(11) > + > +#define TEGRA186_PMC_PLLM_WB0_OVERRIDE_FREQ 0x50 > +#define TEGRA186_PMC_PLLM_WB0_OVERRIDE_2 0x54 > + > #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) > #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) > #define PMC_SCRATCH0_MODE_RCM BIT(1) > @@ -122,6 +130,9 @@ > #define IO_DPD2_STATUS 0x1c4 > #define SEL_DPD_TIM 0x1c8 > > +#define PMC_PLLM_WB0_OVERRIDE_FREQ 0x1dc > +#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 > + > #define PMC_SCRATCH54 0x258 > #define PMC_SCRATCH54_DATA_SHIFT 8 > #define PMC_SCRATCH54_ADDR_SHIFT 0 > @@ -182,6 +193,15 @@ struct tegra_pmc_regs { > unsigned int rst_source_mask; > unsigned int rst_level_shift; > unsigned int rst_level_mask; > + unsigned int pllp_wb0_override; > + unsigned int pllm_wb0_override_freq; > + unsigned int pllm_wb0_override_2; > + unsigned int override_divm_shift; > + unsigned int override_divm_mask; > + unsigned int override_divn_shift; > + unsigned int override_divn_mask; > + unsigned int override_divp_shift; > + unsigned int override_divp_mask; > }; > > struct tegra_wake_event { > @@ -227,6 +247,7 @@ struct tegra_pmc_soc { > bool needs_mbist_war; > bool has_impl_33v_pwr; > bool maybe_tz_only; > + bool has_pllm_wb0_override; > > const struct tegra_io_pad_soc *io_pads; > unsigned int num_io_pads; > @@ -1156,6 +1177,99 @@ static void tegra_powergate_remove_all(struct device_node *parent) > of_node_put(np); > } > > +bool tegra_pmc_is_pllm_wb0_override_enabled(void) > +{ > + u32 val; > + > + if (pmc->soc->has_pllm_wb0_override) { > + val = tegra_pmc_readl(pmc, pmc->soc->regs->pllp_wb0_override); > + return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) ? 1 : 0; > + } > + > + return 0; > +} > +EXPORT_SYMBOL(tegra_pmc_is_pllm_wb0_override_enabled); > + > +bool tegra_pmc_is_pllm_wb0_enabled(void) > +{ > + u32 val; > + > + if (pmc->soc->has_pllm_wb0_override) { > + val = tegra_pmc_readl(pmc, pmc->soc->regs->pllp_wb0_override); > + return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? 1 : 0; > + } > + > + return 0; > +} > +EXPORT_SYMBOL(tegra_pmc_is_pllm_wb0_enabled); > + > +void tegra_pmc_set_pllm_wb0_enable(bool enable) > +{ > + u32 val; > + > + if (pmc->soc->has_pllm_wb0_override) { > + val = tegra_pmc_readl(pmc, pmc->soc->regs->pllp_wb0_override); > + if (enable) > + val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; > + else > + val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; > + tegra_pmc_writel(pmc, val, pmc->soc->regs->pllp_wb0_override); > + } > +} > +EXPORT_SYMBOL(tegra_pmc_set_pllm_wb0_enable); > + > +void tegra_pmc_get_pllm_wb0_mnp_overrides(u32 *divm, u32 *divn, u8 *divp) > +{ > + u32 val; > + unsigned int divnm_reg, divp_reg; > + > + if (pmc->soc->has_pllm_wb0_override) { > + divnm_reg = pmc->soc->regs->pllm_wb0_override_freq; > + divp_reg = pmc->soc->regs->pllm_wb0_override_2; > + > + if (tegra_pmc_is_pllm_wb0_override_enabled()) { > + val = tegra_pmc_readl(pmc, divnm_reg); > + *divm = (val >> pmc->soc->regs->override_divm_shift) & > + pmc->soc->regs->override_divm_mask; > + *divn = (val >> pmc->soc->regs->override_divn_shift) & > + pmc->soc->regs->override_divn_mask; > + val = tegra_pmc_readl(pmc, divp_reg); > + *divp = (val >> pmc->soc->regs->override_divp_shift) & > + pmc->soc->regs->override_divp_mask; > + } > + } > +} > +EXPORT_SYMBOL(tegra_pmc_get_pllm_wb0_mnp_overrides); > + > +void tegra_pmc_set_pllm_wb0_mnp_overrides(u32 divm, u32 divn, u8 divp) > +{ > + u32 val; > + unsigned int divnm_reg, divp_reg; > + > + if (pmc->soc->has_pllm_wb0_override) { > + divnm_reg = pmc->soc->regs->pllm_wb0_override_freq; > + divp_reg = pmc->soc->regs->pllm_wb0_override_2; > + > + if (tegra_pmc_is_pllm_wb0_override_enabled()) { > + val = tegra_pmc_readl(pmc, divp_reg); > + val &= ~(pmc->soc->regs->override_divp_mask << > + pmc->soc->regs->override_divp_shift); > + val |= (divp << pmc->soc->regs->override_divp_shift); > + tegra_pmc_writel(pmc, val, divp_reg); > + > + val = tegra_pmc_readl(pmc, divnm_reg); > + val &= ~(pmc->soc->regs->override_divm_mask << > + pmc->soc->regs->override_divm_shift); > + val |= divm << pmc->soc->regs->override_divm_shift; > + val &= ~(pmc->soc->regs->override_divn_mask << > + pmc->soc->regs->override_divn_shift); > + val |= divn << pmc->soc->regs->override_divn_shift; > + tegra_pmc_writel(pmc, val, divnm_reg); > + } > + } > +} > +EXPORT_SYMBOL(tegra_pmc_set_pllm_wb0_mnp_overrides); Hello Sowjanya, The exporting isn't needed because both PMC and CaR drivers are built-in. Same for the other patches. [snip]