Received: by 2002:a25:7ec1:0:0:0:0:0 with SMTP id z184csp1013874ybc; Tue, 19 Nov 2019 13:01:31 -0800 (PST) X-Google-Smtp-Source: APXvYqyCL3pETbgOsXPIug7JlRLkzthmMUai857NJgZyUILHtpgkxb3J4+aXnSUZoap88xOVTw6y X-Received: by 2002:a17:906:698b:: with SMTP id i11mr36735673ejr.97.1574197291473; Tue, 19 Nov 2019 13:01:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574197291; cv=none; d=google.com; s=arc-20160816; b=STWQIT+F2xXi8SjQmHlkC0c7DwRCxszndBCpVCPfJS82eF1QtoYFVLKuyja1feKqar f0O4H/PQzkItSArVZF0DkLqaFf/EvWNPzk9X8hSawLNgJBz6Mv5f1Hi0DkcUPTN1nOoD fuYnCCeInec8mFejHR82Q2uTXeMq3uid5Rxsmo/Bwxto6aPI8VDNJe4La4OdcsRbTWCA RlPJzTqy9RuJ3OKLiePB23uNi2l3oEYCB1SmhpGBnW8UNxfN3xaUXkXRLfGxdsDbOhxQ bXZytJuon3KPSoyGfwu7IVqqTRoXqNTYutKjYSn9MH3KNvLkmqplY/e9Yo1XcgfXKows KRrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:organization:from:references:cc:to:subject; bh=6ykMCTIaRqhfG90Oevd7zUkrYFxp63Bz2CzV8dC3/+I=; b=stxxCXN/66ejlPj26W+qIZbGl4GiT6YlwERwhzDxcFqvVc8PP4CGM6KQrzi20BBJQ7 DYSKj89jQUiI0TptMQ/QNcwJCLZ/ts2CdExPq4WuDZEVHHC4NH5jt0LQlFrJfodRhMXS UKdp4r6j/cbywtwoL6z8r4l2wLM2ZSx/aW7MHQnhklIP3+v2RM7GXvatp7rz7YoKfHnL /+tM8DbxxXMWKK7NGu2N+xtcx/vRfLJRfNTAkQkCUzpD5U+841GBMj9mXMN3onXGYH1R HvyJxN2axGElbmwyAG8AQTifmD6AnLT00EGEziyhjRWI+/uA3+JQPn/rGmd6NuX1vFst iMNw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d14si15218328ejc.72.2019.11.19.13.01.03; Tue, 19 Nov 2019 13:01:31 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727118AbfKSU4w (ORCPT + 99 others); Tue, 19 Nov 2019 15:56:52 -0500 Received: from mx2.suse.de ([195.135.220.15]:50354 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726711AbfKSU4v (ORCPT ); Tue, 19 Nov 2019 15:56:51 -0500 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 4F97FAC84; Tue, 19 Nov 2019 20:56:50 +0000 (UTC) Subject: Re: [PATCH v4 2/8] irqchip: Add Realtek RTD1295 mux driver To: Marc Zyngier Cc: linux-realtek-soc@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Aleix Roca Nonell , James Tai , Thomas Gleixner , Jason Cooper References: <20191119021917.15917-1-afaerber@suse.de> <20191119021917.15917-3-afaerber@suse.de> From: =?UTF-8?Q?Andreas_F=c3=a4rber?= Organization: SUSE Software Solutions Germany GmbH Message-ID: Date: Tue, 19 Nov 2019 21:56:48 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am 19.11.19 um 13:01 schrieb Marc Zyngier: > On 2019-11-19 02:19, Andreas Färber wrote: >> +static void rtd1195_mux_enable_irq(struct irq_data *data) >> +{ >> +    struct rtd1195_irq_mux_data *mux_data = >> irq_data_get_irq_chip_data(data); >> +    unsigned long flags; >> +    u32 mask; >> + >> +    mask = mux_data->info->isr_to_int_en_mask[data->hwirq]; >> +    if (!mask) >> +        return; > > How can this happen? You've mapped the interrupt, so it exists. > I can't see how you can decide to fail such enable. The [UMSK_]ISR bits and the SCPU_INT_EN bits are not (all) the same. My ..._isr_to_scpu_int_en[] arrays have 32 entries for O(1) lookup, but are sparsely populated. So there are circumstances such as WDOG_NMI as well as reserved bits that we cannot enable. This check should be identical to v3; the equivalent mask check inside the interrupt handler was extended with "mask &&" to do the same in this v4. The other question I'll need to dig into, it's been two years since I wrote that code - first very simple guesswork, then more elaborate quirks like the above. Regards, Andreas -- SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Felix Imendörffer HRB 36809 (AG Nürnberg)