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Date:   Wed, 20 Nov 2019 12:45:38 +0100
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH 2/2 v3] MIPS: Ingenic: Disable abandoned HPTLB function.
To:     Zhou Yanjie <zhouyanjie@zoho.com>
Cc:     linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
        ralf@linux-mips.org, paulburton@kernel.org, jhogan@kernel.org,
        jiaxun.yang@flygoat.com, gregkh@linuxfoundation.org,
        malat@debian.org, tglx@linutronix.de, chenhc@lemote.com
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Hi Zhou,


Le mar., nov. 19, 2019 at 22:28, Zhou Yanjie <zhouyanjie@zoho.com> a=20
=E9crit :
> JZ4760/JZ4770/JZ4775/X1000/X1500 has an abandoned huge page tlb,
> this mode is not compatible with the MIPS standard, it will cause
> tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
> when starting the init process. write 0xa9000000 to cp0 register 5
> sel 4 to disable this function to prevent getting stuck. Confirmed
> by Ingenic, this operation will not adversely affect processors
> without HPTLB function.
>=20
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>

Acked-by: Paul Cercueil <paul@crapouillou.net>

> ---
>  arch/mips/include/asm/mipsregs.h |  6 ++++++
>  arch/mips/kernel/cpu-probe.c     | 21 +++++++++++++++++++--
>  2 files changed, 25 insertions(+), 2 deletions(-)

Still no changelog here :)


> diff --git a/arch/mips/include/asm/mipsregs.h=20
> b/arch/mips/include/asm/mipsregs.h
> index bdbdc19..0d5a309 100644
> --- a/arch/mips/include/asm/mipsregs.h
> +++ b/arch/mips/include/asm/mipsregs.h
> @@ -689,6 +689,9 @@
>  #define MIPS_CONF7_IAR		(_ULCAST_(1) << 10)
>  #define MIPS_CONF7_AR		(_ULCAST_(1) << 16)
>=20
> +/* Ingenic HPTLB off bits */
> +#define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
> +
>  /* Ingenic Config7 bits */
>  #define MIPS_CONF7_BTB_LOOP_EN	(_ULCAST_(1) << 4)
>=20
> @@ -1971,6 +1974,9 @@ do {									\
>  #define read_c0_brcm_sleepcount()	__read_32bit_c0_register($22, 7)
>  #define write_c0_brcm_sleepcount(val)	__write_32bit_c0_register($22,=20
> 7, val)
>=20
> +/* Ingenic page ctrl register */
> +#define write_c0_page_ctrl(val)	__write_32bit_c0_register($5, 4, val)
> +
>  /*
>   * Macros to access the guest system control coprocessor
>   */
> diff --git a/arch/mips/kernel/cpu-probe.c=20
> b/arch/mips/kernel/cpu-probe.c
> index 7a0e33c..3b5f4fb 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -1965,13 +1965,30 @@ static inline void cpu_probe_ingenic(struct=20
> cpuinfo_mips *c, unsigned int cpu)
>  		break;
>  	}
>=20
> +	switch (c->processor_id & PRID_COMP_MASK) {
> +	/*
> +	 * The config0 register in the XBurst CPUs with a processor ID of
> +	 * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
> +	 * mode is not compatible with the MIPS standard, it will cause
> +	 * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
> +	 * when starting the init process. After chip reset, the default
> +	 * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
> +	 * switch back to VTLB mode to prevent getting stuck.
> +	 */
> +	case PRID_COMP_INGENIC_D1:
> +		write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
> +		break;
>  	/*
> -	 * The config0 register in the Xburst CPUs with a processor ID of
> +	 * The config0 register in the XBurst CPUs with a processor ID of
>  	 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
>  	 * but they don't actually support this ISA.
>  	 */
> -	if ((c->processor_id & PRID_COMP_MASK) =3D=3D PRID_COMP_INGENIC_D0)
> +	case PRID_COMP_INGENIC_D0:
>  		c->isa_level &=3D ~MIPS_CPU_ISA_M32R2;
> +		break;
> +	default:
> +		break;
> +	}
>  }
>=20
>  static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int=20
> cpu)
> --
> 2.7.4
>=20
>=20

=