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[209.132.180.67]) by mx.google.com with ESMTP id oy25si15419487ejb.291.2019.11.20.05.41.10; Wed, 20 Nov 2019 05:41:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728335AbfKTNVJ (ORCPT + 99 others); Wed, 20 Nov 2019 08:21:09 -0500 Received: from Galois.linutronix.de ([193.142.43.55]:56658 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727783AbfKTNVI (ORCPT ); Wed, 20 Nov 2019 08:21:08 -0500 Received: from [5.158.153.53] (helo=tip-bot2.lab.linutronix.de) by Galois.linutronix.de with esmtpsa (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iXPup-00075u-GN; Wed, 20 Nov 2019 14:21:03 +0100 Received: from [127.0.1.1] (localhost [IPv6:::1]) by tip-bot2.lab.linutronix.de (Postfix) with ESMTP id 2C7761C1A01; Wed, 20 Nov 2019 14:21:02 +0100 (CET) Date: Wed, 20 Nov 2019 13:21:02 -0000 From: "tip-bot2 for Zhou Yanjie" Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: irq/core] irqchip: Ingenic: Add process for more than one irq at the same time. Cc: Zhou Yanjie , Marc Zyngier , Paul Cercueil , Ingo Molnar , Borislav Petkov , linux-kernel@vger.kernel.org In-Reply-To: <1570015525-27018-6-git-send-email-zhouyanjie@zoho.com> References: <1570015525-27018-6-git-send-email-zhouyanjie@zoho.com> MIME-Version: 1.0 Message-ID: <157425606206.12247.3466209751027396364.tip-bot2@tip-bot2> X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/core branch of tip: Commit-ID: b8b0145f7d0e24d98a58b7e54051dca0c1d77526 Gitweb: https://git.kernel.org/tip/b8b0145f7d0e24d98a58b7e54051dca0c1d77526 Author: Zhou Yanjie AuthorDate: Wed, 02 Oct 2019 19:25:25 +08:00 Committer: Marc Zyngier CommitterDate: Sun, 10 Nov 2019 18:55:31 irqchip: Ingenic: Add process for more than one irq at the same time. Add process for the situation that more than one irq is coming to a single chip at the same time. The original code will only respond to the lowest setted bit in JZ_REG_INTC_PENDING, and then exit the interrupt dispatch function. After exiting the interrupt dispatch function, since the second interrupt has not yet responded, the interrupt dispatch function is again entered to process the second interrupt. This creates additional unnecessary overhead, and the more interrupts that occur at the same time, the more overhead is added. The improved method in this patch is to check whether there are still unresponsive interrupts after processing the lowest setted bit interrupt. If there are any, the processing will be processed according to the bit in JZ_REG_INTC_PENDING, and the interrupt dispatch function will be exited until all processing is completed. Signed-off-by: Zhou Yanjie Signed-off-by: Marc Zyngier Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/1570015525-27018-6-git-send-email-zhouyanjie@zoho.com --- drivers/irqchip/irq-ingenic.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c index 06ab3ad..01d18b3 100644 --- a/drivers/irqchip/irq-ingenic.c +++ b/drivers/irqchip/irq-ingenic.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2009-2010, Lars-Peter Clausen - * JZ4740 platform IRQ support + * Ingenic XBurst platform IRQ support */ #include @@ -37,18 +37,23 @@ static irqreturn_t intc_cascade(int irq, void *data) struct ingenic_intc_data *intc = irq_get_handler_data(irq); struct irq_domain *domain = intc->domain; struct irq_chip_generic *gc; - uint32_t irq_reg; + uint32_t pending; unsigned i; for (i = 0; i < intc->num_chips; i++) { gc = irq_get_domain_generic_chip(domain, i * 32); - irq_reg = irq_reg_readl(gc, JZ_REG_INTC_PENDING); - if (!irq_reg) + pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING); + if (!pending) continue; - irq = irq_find_mapping(domain, __fls(irq_reg) + (i * 32)); - generic_handle_irq(irq); + while (pending) { + int bit = __fls(pending); + + irq = irq_find_mapping(domain, bit + (i * 32)); + generic_handle_irq(irq); + pending &= ~BIT(bit); + } } return IRQ_HANDLED;