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Date:   Wed, 20 Nov 2019 15:08:26 +0200
From:   Andy Shevchenko <andriy.shevchenko@intel.com>
To:     Dilip Kota <eswara.kota@linux.intel.com>
Cc:     gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com,
        andrew.murray@arm.com, helgaas@kernel.org, jingoohan1@gmail.com,
        robh@kernel.org, martin.blumenstingl@googlemail.com,
        linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, cheol.yong.kim@intel.com,
        chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com
Subject: Re: [PATCH v8 2/3] dwc: PCI: intel: PCIe RC controller driver
Message-ID: <20191120130826.GM32742@smile.fi.intel.com>
References: <cover.1574158309.git.eswara.kota@linux.intel.com>
 <71262d29ca564060331e7e2c1ceb41158109cb92.1574158309.git.eswara.kota@linux.intel.com>
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On Wed, Nov 20, 2019 at 03:43:01PM +0800, Dilip Kota wrote:
> Add support to PCIe RC controller on Intel Gateway SoCs.
> PCIe controller is based of Synopsys DesignWare PCIe core.
> 
> Intel PCIe driver requires Upconfigure support, Fast Training
> Sequence and link speed configurations. So adding the respective
> helper functions in the PCIe DesignWare framework.
> It also programs hardware autonomous speed during speed
> configuration so defining it in pci_regs.h.

> +static void pcie_app_wr_mask(struct intel_pcie_port *lpp,
> +			     u32 ofs, u32 mask, u32 val)

It seems your editor is misconfigured. First line should be

static void pcie_app_wr_mask(struct intel_pcie_port *lpp, u32 ofs,

in case you would like to split it logically.

> +static void pcie_rc_cfg_wr_mask(struct intel_pcie_port *lpp,
> +				u32 ofs, u32 mask, u32 val)

Ditto.

> +	pcie_app_wr(lpp,  PCIE_APP_IRNCR, PCIE_APP_IRN_INT);

Extra white space.

-- 
With Best Regards,
Andy Shevchenko