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Subject: Re: [PATCH v3 2/8] iommu/vt-d: Match CPU and IOMMU paging mode
To:     Jacob Pan <jacob.jun.pan@linux.intel.com>,
        iommu@lists.linux-foundation.org,
        LKML <linux-kernel@vger.kernel.org>,
        Joerg Roedel <joro@8bytes.org>,
        Lu Baolu <baolu.lu@linux.intel.com>,
        David Woodhouse <dwmw2@infradead.org>
Cc:     "Tian, Kevin" <kevin.tian@intel.com>,
        Raj Ashok <ashok.raj@intel.com>, Yi Liu <yi.l.liu@intel.com>,
        "Mehta, Sohil" <sohil.mehta@intel.com>
References: <1574186193-30457-1-git-send-email-jacob.jun.pan@linux.intel.com>
 <1574186193-30457-3-git-send-email-jacob.jun.pan@linux.intel.com>
From:   Auger Eric <eric.auger@redhat.com>
Message-ID: <c77782e3-fafa-6397-94e0-e0be8572acd3@redhat.com>
Date:   Wed, 20 Nov 2019 22:08:39 +0100
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Hi Jacob,
On 11/19/19 6:56 PM, Jacob Pan wrote:
> When setting up first level page tables for sharing with CPU, we need
> to ensure IOMMU can support no less than the levels supported by the
> CPU.
>=20
> It is not adequate, as in the current code, to set up 5-level paging
> in PASID entry First Level Paging Mode(FLPM) solely based on CPU.
>=20
> Currently, intel_pasid_setup_first_level() is only used by native SVM
> code which already checks paging mode matches. However, future use of
> this helper function may not be limited to native SVM.
> https://lkml.org/lkml/2019/11/18/1037
>=20
> Fixes: 437f35e1cd4c8 ("iommu/vt-d: Add first level page table
> interface")
> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
> Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Thanks

Eric
> ---
>  drivers/iommu/intel-pasid.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
> index 040a445be300..e7cb0b8a7332 100644
> --- a/drivers/iommu/intel-pasid.c
> +++ b/drivers/iommu/intel-pasid.c
> @@ -499,8 +499,16 @@ int intel_pasid_setup_first_level(struct intel_iommu=
 *iommu,
>  =09}
> =20
>  #ifdef CONFIG_X86
> -=09if (cpu_feature_enabled(X86_FEATURE_LA57))
> -=09=09pasid_set_flpm(pte, 1);
> +=09/* Both CPU and IOMMU paging mode need to match */
> +=09if (cpu_feature_enabled(X86_FEATURE_LA57)) {
> +=09=09if (cap_5lp_support(iommu->cap)) {
> +=09=09=09pasid_set_flpm(pte, 1);
> +=09=09} else {
> +=09=09=09pr_err("VT-d has no 5-level paging support for CPU\n");
> +=09=09=09pasid_clear_entry(pte);
> +=09=09=09return -EINVAL;
> +=09=09}
> +=09}
>  #endif /* CONFIG_X86 */
> =20
>  =09pasid_set_domain_id(pte, did);
>=20