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From:   =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
To:     linux-realtek-soc@lists.infradead.org
Cc:     linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>,
        Thomas Gleixner <tglx@linutronix.de>,
        Jason Cooper <jason@lakedaemon.net>,
        Marc Zyngier <maz@kernel.org>
Subject: [PATCH v5 3/9] irqchip: rtd1195-mux: Implement irq_get_irqchip_state
Date:   Thu, 21 Nov 2019 06:02:02 +0100
Message-Id: <20191121050208.11324-4-afaerber@suse.de>
In-Reply-To: <20191121050208.11324-1-afaerber@suse.de>
References: <20191121050208.11324-1-afaerber@suse.de>
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Sender: linux-kernel-owner@vger.kernel.org
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Implement the .irq_get_irqchip_state callback to retrieve pending,
active and masked interrupt status.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v5: New
 
 drivers/irqchip/irq-rtd1195-mux.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/irqchip/irq-rtd1195-mux.c b/drivers/irqchip/irq-rtd1195-mux.c
index 0e86973aafca..2f1bcfd9d5d6 100644
--- a/drivers/irqchip/irq-rtd1195-mux.c
+++ b/drivers/irqchip/irq-rtd1195-mux.c
@@ -7,6 +7,7 @@
 
 #include <linux/bitops.h>
 #include <linux/io.h>
+#include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
@@ -96,10 +97,45 @@ static void rtd1195_mux_unmask_irq(struct irq_data *data)
 	raw_spin_unlock_irqrestore(&mux->lock, flags);
 }
 
+static int rtd1195_mux_get_irqchip_state(struct irq_data *data,
+	enum irqchip_irq_state which, bool *state)
+{
+	struct rtd1195_irq_mux_data *mux = irq_data_get_irq_chip_data(data);
+	u32 val;
+
+	switch (which) {
+	case IRQCHIP_STATE_PENDING:
+		/*
+		 * UMSK_ISR provides the unmasked pending interrupts,
+		 * except UART and I2C.
+		 */
+		val = readl_relaxed(mux->reg_umsk_isr);
+		*state = !!(val & BIT(data->hwirq));
+		break;
+	case IRQCHIP_STATE_ACTIVE:
+		/*
+		 * ISR provides the masked pending interrupts,
+		 * including UART and I2C.
+		 */
+		val = readl_relaxed(mux->reg_isr);
+		*state = !!(val & BIT(data->hwirq));
+		break;
+	case IRQCHIP_STATE_MASKED:
+		val = mux->info->isr_to_int_en_mask[data->hwirq];
+		*state = !(mux->scpu_int_en & val);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static const struct irq_chip rtd1195_mux_irq_chip = {
 	.irq_ack		= rtd1195_mux_ack_irq,
 	.irq_mask		= rtd1195_mux_mask_irq,
 	.irq_unmask		= rtd1195_mux_unmask_irq,
+	.irq_get_irqchip_state	= rtd1195_mux_get_irqchip_state,
 };
 
 static int rtd1195_mux_irq_domain_map(struct irq_domain *d,
-- 
2.16.4