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From:   "Pankaj Dubey" <pankaj.dubey@samsung.com>
To:     "'Gustavo Pimentel'" <Gustavo.Pimentel@synopsys.com>,
        "'Anvesh Salveru'" <anvesh.s@samsung.com>,
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Subject: RE: [PATCH v4 2/2] PCI: dwc: add support to handle ZRX-DC Compliant
 PHYs
Date:   Fri, 22 Nov 2019 08:05:25 +0530
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> -----Original Message-----
> From: Gustavo Pimentel <Gustavo.Pimentel=40synopsys.com>
> Sent: Thursday, November 21, 2019 7:25 PM
> To: Anvesh Salveru <anvesh.s=40samsung.com>; linux-kernel=40vger.kernel.o=
rg;
> linux-pci=40vger.kernel.org
> Cc: jingoohan1=40gmail.com; pankaj.dubey=40samsung.com;
> lorenzo.pieralisi=40arm.com; andrew.murray=40arm.com; bhelgaas=40google.c=
om;
> kishon=40ti.com; robh+dt=40kernel.org; mark.rutland=40arm.com
> Subject: RE: =5BPATCH v4 2/2=5D PCI: dwc: add support to handle ZRX-DC Co=
mpliant
> PHYs
>=20
> On Thu, Nov 21, 2019 at 3:20:8, Anvesh Salveru <anvesh.s=40samsung.com>
> wrote:
>=20
> > Many platforms use DesignWare controller but the PHY can be different
> > in different platforms. If the PHY is compliant is to ZRX-DC
> > specification it helps in low power consumption during power states.
> >
> > If current data rate is 8.0 GT/s or higher and PHY is not compliant to
> > ZRX-DC specification, then after every 100ms link should transition to
> > recovery state during the low power states.
> >
> > DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
> > GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
> >
> > Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant
> > variable to specify this property to the controller.
> >
> > Signed-off-by: Anvesh Salveru <anvesh.s=40samsung.com>
> > Signed-off-by: Pankaj Dubey <pankaj.dubey=40samsung.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-designware.c =7C 6 ++++++
> > drivers/pci/controller/dwc/pcie-designware.h =7C 4 ++++
> >  2 files changed, 10 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c
> > b/drivers/pci/controller/dwc/pcie-designware.c
> > index 820488d..36a01b7 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > =40=40 -556,4 +556,10 =40=40 void dw_pcie_setup(struct dw_pcie *pci)
> >  		       PCIE_PL_CHK_REG_CHK_REG_START;
> >  		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS,
> val);
> >  	=7D
> > +
> > +	if (pci->phy_zrxdc_compliant) =7B
> > +		val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
> > +		val &=3D =7EPORT_LOGIC_GEN3_ZRXDC_NONCOMPL;
> > +		dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
> > +	=7D
> >  =7D
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> > b/drivers/pci/controller/dwc/pcie-designware.h
> > index 5a18e94..f43f986 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > =40=40 -60,6 +60,9 =40=40
> >  =23define PCIE_MSI_INTR0_MASK		0x82C
> >  =23define PCIE_MSI_INTR0_STATUS		0x830
> >
> > +=23define PCIE_PORT_GEN3_RELATED		0x890
> > +=23define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL	BIT(0)
> > +
> >  =23define PCIE_ATU_VIEWPORT		0x900
> >  =23define PCIE_ATU_REGION_INBOUND		BIT(31)
> >  =23define PCIE_ATU_REGION_OUTBOUND	0
> > =40=40 -249,6 +252,7 =40=40 struct dw_pcie =7B
> >  	void __iomem		*atu_base;
> >  	u32			num_viewport;
> >  	u8			iatu_unroll_enabled;
> > +	bool			phy_zrxdc_compliant;
>=20
> Typically is used u8 instead of bool, due to platform compatibility.
> I'd guess that checkpatch script should have reported this. Did you use i=
t?

Checkpatch didn't report any error/warning.=20
We used bool here as phy_zrxdc_compliant will store the value returned by o=
f_property_read_bool API.=20
I can see many places in drivers/pci/ where this API is used the value is s=
tored in bool itself.

>=20
> >  	struct pcie_port	pp;
> >  	struct dw_pcie_ep	ep;
> >  	const struct dw_pcie_ops *ops;
> > --
> > 2.7.4
>=20