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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Abel Vesa <abel.vesa@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
        Stephen Boyd <sboyd@kernel.org>
CC:     Aisheng Dong <aisheng.dong@nxp.com>,
        Sascha Hauer <kernel@pengutronix.de>,
        Jacky Bai <ping.bai@nxp.com>, Peng Fan <peng.fan@nxp.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 01/11] clk: imx: Add correct failure handling for clk
 based helpers
Thread-Topic: [PATCH v2 01/11] clk: imx: Add correct failure handling for clk
 based helpers
Thread-Index: AQHVoSJWiPUbLE4/j0WIQrxGUo4alw==
Date:   Fri, 22 Nov 2019 21:48:25 +0000
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References: <1574419679-3813-1-git-send-email-abel.vesa@nxp.com>
 <1574419679-3813-2-git-send-email-abel.vesa@nxp.com>
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On 2019-11-22 12:48 PM, Abel Vesa wrote:=0A=
> If the clk_hw based API returns an error, trying to return the clk from=
=0A=
> hw will end up in a NULL pointer dereference. So adding the to_clk=0A=
> checker and using it inside every clk based macro helper we handle that=
=0A=
> case correctly.=0A=
> =0A=
> This to_clk is also temporary and will go away along with the clk based=
=0A=
> macro helpers once there is no user that need them anymore.=0A=
> =0A=
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>=0A=
=0A=
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>=0A=
=0A=
> ---=0A=
>   drivers/clk/imx/clk.h | 37 ++++++++++++++++++++++---------------=0A=
>   1 file changed, 22 insertions(+), 15 deletions(-)=0A=
> =0A=
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h=0A=
> index bc5bb6a..30ddbc1 100644=0A=
> --- a/drivers/clk/imx/clk.h=0A=
> +++ b/drivers/clk/imx/clk.h=0A=
> @@ -54,48 +54,48 @@ extern struct imx_pll14xx_clk imx_1416x_pll;=0A=
>   extern struct imx_pll14xx_clk imx_1443x_pll;=0A=
>   =0A=
>   #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \=0A=
> -	imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk=0A=
> +	to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))=0A=
>   =0A=
>   #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx,=
 \=0A=
>   				cgr_val, clk_gate_flags, lock, share_count) \=0A=
> -	clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \=0A=
> -				cgr_val, clk_gate_flags, lock, share_count)->clk=0A=
> +	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_id=
x, \=0A=
> +				cgr_val, clk_gate_flags, lock, share_count))=0A=
>   =0A=
>   #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \=0A=
> -	imx_clk_hw_pllv3(type, name, parent_name, base, div_mask)->clk=0A=
> +	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))=0A=
>   =0A=
>   #define imx_clk_pfd(name, parent_name, reg, idx) \=0A=
> -	imx_clk_hw_pfd(name, parent_name, reg, idx)->clk=0A=
> +	to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))=0A=
>   =0A=
>   #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask=
) \=0A=
> -	imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->cl=
k=0A=
> +	to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_ma=
sk))=0A=
>   =0A=
>   #define imx_clk_fixed_factor(name, parent, mult, div) \=0A=
> -	imx_clk_hw_fixed_factor(name, parent, mult, div)->clk=0A=
> +	to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))=0A=
>   =0A=
>   #define imx_clk_divider2(name, parent, reg, shift, width) \=0A=
> -	imx_clk_hw_divider2(name, parent, reg, shift, width)->clk=0A=
> +	to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))=0A=
>   =0A=
>   #define imx_clk_gate_dis(name, parent, reg, shift) \=0A=
> -	imx_clk_hw_gate_dis(name, parent, reg, shift)->clk=0A=
> +	to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))=0A=
>   =0A=
>   #define imx_clk_gate2(name, parent, reg, shift) \=0A=
> -	imx_clk_hw_gate2(name, parent, reg, shift)->clk=0A=
> +	to_clk(imx_clk_hw_gate2(name, parent, reg, shift))=0A=
>   =0A=
>   #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \=0A=
> -	imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk=0A=
> +	to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))=0A=
>   =0A=
>   #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \=
=0A=
> -	imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk=0A=
> +	to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))=
=0A=
>   =0A=
>   #define imx_clk_gate3(name, parent, reg, shift) \=0A=
> -	imx_clk_hw_gate3(name, parent, reg, shift)->clk=0A=
> +	to_clk(imx_clk_hw_gate3(name, parent, reg, shift))=0A=
>   =0A=
>   #define imx_clk_gate4(name, parent, reg, shift) \=0A=
> -	imx_clk_hw_gate4(name, parent, reg, shift)->clk=0A=
> +	to_clk(imx_clk_hw_gate4(name, parent, reg, shift))=0A=
>   =0A=
>   #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \=0A=
> -	imx_clk_hw_mux(name, reg, shift, width, parents, num_parents)->clk=0A=
> +	to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))=
=0A=
>   =0A=
>   struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,=
=0A=
>   		 void __iomem *base, const struct imx_pll14xx_clk *pll_clk);=0A=
> @@ -198,6 +198,13 @@ struct clk_hw *imx_clk_hw_fixup_mux(const char *name=
, void __iomem *reg,=0A=
>   			      u8 shift, u8 width, const char * const *parents,=0A=
>   			      int num_parents, void (*fixup)(u32 *val));=0A=
>   =0A=
> +static inline struct clk *to_clk(struct clk_hw *hw)=0A=
> +{=0A=
> +	if (IS_ERR_OR_NULL(hw))=0A=
> +		return ERR_CAST(hw);=0A=
> +	return hw->clk;=0A=
> +}=0A=
> +=0A=
>   static inline struct clk *imx_clk_fixed(const char *name, int rate)=0A=
>   {=0A=
>   	return clk_register_fixed_rate(NULL, name, NULL, 0, rate);=0A=
> =0A=
=0A=