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Date:   Fri, 22 Nov 2019 18:46:56 -0600
From:   Rob Herring <robh@kernel.org>
To:     Ran Wang <ran.wang_1@nxp.com>
Cc:     Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Peter Chen <peter.chen@nxp.com>, Jun Li <jun.li@nxp.com>,
        Leo Li <leoyang.li@nxp.com>, linux-usb@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Ran Wang <ran.wang_1@nxp.com>
Subject: Re: [PATCH v3 1/2] usb: dwc3: Add chip-specific compatible string
Message-ID: <20191123004656.GA23783@bogus>
References: <20191121024206.32933-1-ran.wang_1@nxp.com>
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On Thu, 21 Nov 2019 10:42:05 +0800, Ran Wang wrote:
> Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW
> default cache type configuration to fix DWC3 init failure when applying
> property dma-coherent.
> 
> Note that the cache type configuration is actually native feature of DWC3,
> not additional desgin coming from SoC, so add this support here.
> 
> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> ---
> Change in v3:
> 	- Update commit subject according to content change, originanl one is
> 	  'usb: dwc3: Add node to update cache type setting'
> 	- Replace sub-node definition with chip-specifc compatible string.
> 
> Change in v2:
> 	- New file.
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>