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From:   Iuliana Prodan <iuliana.prodan@nxp.com>
To:     Horia Geanta <horia.geanta@nxp.com>,
        Herbert Xu <herbert@gondor.apana.org.au>,
        Aymen Sghaier <aymen.sghaier@nxp.com>
CC:     "David S. Miller" <davem@davemloft.net>,
        "linux-crypto@vger.kernel.org" <linux-crypto@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        dl-linux-imx <linux-imx@nxp.com>,
        Andrey Smirnov <andrew.smirnov@gmail.com>,
        Alison Wang <alison.wang@nxp.com>
Subject: Re: [PATCH] crypto: caam - do not reset pointer size if caam_ptr_size
 is 64 bits
Thread-Topic: [PATCH] crypto: caam - do not reset pointer size if
 caam_ptr_size is 64 bits
Thread-Index: AQHVoxct9YNV/+sCCkCTnpGbBimKsg==
Date:   Mon, 25 Nov 2019 12:02:38 +0000
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On 11/25/2019 9:49 AM, Horia Geanta wrote:=0A=
> On 11/25/2019 12:33 AM, Iuliana Prodan wrote:=0A=
>> In commit 'a1cf573ee95 ("crypto: caam - select DMA address=0A=
>> size at runtime")' CAAM pointer size (caam_ptr_size) is changed=0A=
>> from sizeof(dma_addr_t) to runtime value computed from MCFGR register.=
=0A=
>> At some point, the bit for Pointer Size should be reset to 0,=0A=
>> but only for the case when the CAAM pointer size if 32 bits.=0A=
>> Therefore, use caam_ptr_size instead of sizeof(dma_addr_t).=0A=
>>=0A=
> The logic is circular, see below.=0A=
> =0A=
>> Fixes: a1cf573ee95 ("crypto: caam - select DMA address size at runtime")=
=0A=
> Please Cc the author(s) when adding Fixes tag.=0A=
> =0A=
>> Cc: <stable@vger.kernel.org>=0A=
>> Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>=0A=
>> ---=0A=
>>   drivers/crypto/caam/ctrl.c | 2 +-=0A=
>>   1 file changed, 1 insertion(+), 1 deletion(-)=0A=
>>=0A=
>> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c=0A=
>> index d7c3c38..786eef6 100644=0A=
>> --- a/drivers/crypto/caam/ctrl.c=0A=
>> +++ b/drivers/crypto/caam/ctrl.c=0A=
>> @@ -674,7 +674,7 @@ static int caam_probe(struct platform_device *pdev)=
=0A=
>>   		clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,=0A=
>>   			      MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |=0A=
>>   			      MCFGR_WDENABLE | MCFGR_LARGE_BURST |=0A=
>> -			      (sizeof(dma_addr_t) =3D=3D sizeof(u64) ?=0A=
>> +			      (caam_ptr_sz =3D=3D sizeof(u64) ?=0A=
>>   			       MCFGR_LONG_PTR : 0));=0A=
>>   =0A=
> Before this in caam_probe() there's:=0A=
> 	if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)=
=0A=
> 		caam_ptr_sz =3D sizeof(u64);=0A=
> 	else=0A=
> 		caam_ptr_sz =3D sizeof(u32);=0A=
> =0A=
> thus caam_ptr_sz is determined based on MCFGR:=0A=
> MCFGR[PS] =3D=3D> caam_ptr_sz=0A=
> so it no longer makes sense to reconfigure MCFGR based on caam_ptr_sz:=0A=
> caam_ptr_sz =3D=3D> MCFGR[PS]=0A=
> =0A=
> The short-term fix would be to no longer touch MCFGR[PS], which is in lin=
e with=0A=
> commit a1cf573ee95 ("crypto: caam - select DMA address size at runtime")=
=0A=
> =0A=
> Note however there's a small issue with the logic of kernel relying on=0A=
> MCFGR[PS] being previously configured (by U-boot etc.), see=0A=
> commit 39eaf759466f ("crypto: caam - fix pointer size for AArch64 boot lo=
ader, AArch32 kernel")=0A=
> =0A=
=0A=
So, what's your suggestion? We shouldn't reset the MCFGR[PS] at all? We =0A=
should use the value set by u-boot?=0A=
=0A=
Thanks,=0A=
Iulia=0A=
=0A=
> In the long run, IMO the proper thing for the driver to do is to rely,=0A=
> whenever possible, on DT ("dma-ranges" property) / dma_mask provided by=
=0A=
> the device driver infrastructure, and not on MCFGR[PS]:=0A=
> [ DT "dma-ranges" =3D=3D> ] dma_mask =3D=3D> MCFGR[PS], caam_ptr_sz=0A=
> but that would probably involve too many changes for getting into -stable=
.=0A=
> =0A=
> Horia=0A=
> =0A=
=0A=