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From:   Clark Wang <xiaoning.wang@nxp.com>
To:     Biwen Li <biwen.li@nxp.com>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "kernel@pengutronix.de" <kernel@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "wsa@the-dreams.de" <wsa@the-dreams.de>,
        Leo Li <leoyang.li@nxp.com>,
        Aisheng Dong <aisheng.dong@nxp.com>,
        "o.rempel@pengutronix.de" <o.rempel@pengutronix.de>
CC:     "linux-i2c@vger.kernel.org" <linux-i2c@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        Laurentiu Tudor <laurentiu.tudor@nxp.com>,
        Jiafei Pan <jiafei.pan@nxp.com>,
        Xiaobo Xie <xiaobo.xie@nxp.com>, Biwen Li <biwen.li@nxp.com>
Subject: RE: [v5] i2c: imx: support slave mode for imx I2C driver
Thread-Topic: [v5] i2c: imx: support slave mode for imx I2C driver
Thread-Index: AQHVppQx3ub2UeJqLEWUL8Z8ZwqGaKeh5l4g
Date:   Fri, 29 Nov 2019 09:55:26 +0000
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> -----Original Message-----
> From: Biwen Li <biwen.li@nxp.com>
> Sent: Friday, November 29, 2019 17:05
> To: shawnguo@kernel.org; s.hauer@pengutronix.de;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx <linux-
> imx@nxp.com>; wsa@the-dreams.de; Leo Li <leoyang.li@nxp.com>;
> Aisheng Dong <aisheng.dong@nxp.com>; Clark Wang
> <xiaoning.wang@nxp.com>; o.rempel@pengutronix.de
> Cc: linux-i2c@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; Laurentiu Tudor <laurentiu.tudor@nxp.com>;
> Jiafei Pan <jiafei.pan@nxp.com>; Xiaobo Xie <xiaobo.xie@nxp.com>; Biwen
> Li <biwen.li@nxp.com>
> Subject: [v5] i2c: imx: support slave mode for imx I2C driver
>=20
> The patch supports slave mode for imx I2C driver
>=20
> Signed-off-by: Biwen Li <biwen.li@nxp.com>
> ---
> Change in v5:
> 	- fix a bug that cannot determine in what mode(master mode or
> 	  slave mode)
>=20
> Change in v4:
> 	- add MACRO CONFIG_I2C_SLAVE to fix compilation issue
>=20
> Change in v3:
> 	- support layerscape and i.mx platform
>=20
> Change in v2:
> 	- remove MACRO CONFIG_I2C_SLAVE
>=20
>=20
>  drivers/i2c/busses/i2c-imx.c | 216
> ++++++++++++++++++++++++++++++++---
>  1 file changed, 198 insertions(+), 18 deletions(-)
>=20
> diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c =
index
> a3b61336fe55..52f70de16900 100644
> --- a/drivers/i2c/busses/i2c-imx.c
> +++ b/drivers/i2c/busses/i2c-imx.c
> @@ -203,6 +203,9 @@ struct imx_i2c_struct {
>  	struct pinctrl_state *pinctrl_pins_gpio;
>=20
>  	struct imx_i2c_dma	*dma;
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> +	struct i2c_client	*slave;
> +#endif
>  };
>=20
>  static const struct imx_i2c_hwdata imx1_i2c_hwdata =3D { @@ -279,6 +282,=
14
> @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct
> *i2c_imx,
>  	return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));  }
>=20
> +/* Set up i2c controller register and i2c status register to default
> +value. */ static void i2c_imx_reset_regs(struct imx_i2c_struct
> +*i2c_imx) {
> +	imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
> +			i2c_imx, IMX_I2C_I2CR);
> +	imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
> +IMX_I2C_I2SR); }
> +
>  /* Functions for DMA support */
>  static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
>  						dma_addr_t phy_addr)
> @@ -588,23 +599,33 @@ static void i2c_imx_stop(struct imx_i2c_struct
> *i2c_imx)
>  	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);  }
>=20
> -static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
> +/* Clear interrupt flag bit */
> +static void i2c_imx_clr_if_bit(unsigned int status, struct
> +imx_i2c_struct *i2c_imx)
>  {
> -	struct imx_i2c_struct *i2c_imx =3D dev_id;
> -	unsigned int temp;
> +	status &=3D ~I2SR_IIF;
> +	status |=3D (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> +	imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
>=20
> -	temp =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> -	if (temp & I2SR_IIF) {
> -		/* save status register */
> -		i2c_imx->i2csr =3D temp;
> -		temp &=3D ~I2SR_IIF;
> -		temp |=3D (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> -		imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
> -		wake_up(&i2c_imx->queue);
> -		return IRQ_HANDLED;
> -	}
> +/* Clear arbitration lost bit */
> +static void i2c_imx_clr_al_bit(unsigned int status, struct
> +imx_i2c_struct *i2c_imx) {
> +	status &=3D ~I2SR_IAL;
> +	status |=3D (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IAL);
> +	imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
>=20
> -	return IRQ_NONE;
> +static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx) {
> +	unsigned int status;
> +
> +	/* Save status register */
> +	status =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> +	i2c_imx->i2csr =3D status | I2SR_IIF;
> +
> +	wake_up(&i2c_imx->queue);
> +
> +	return IRQ_HANDLED;
>  }

Hi Biwen,

We only use i2c_imx->i2csr for IIF judgement in i2c_imx_trx_complete(), can=
 we use this code:
static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx)
{
	i2c_imx->i2csr =3D I2SR_IIF;

	wake_up(&i2c_imx->queue);

	return IRQ_HANDLED;
}
Or even put these three lines to isr function directly?=20
i2c_imx_master_isr() is only called when if (status & I2SR_IIF) is true, so=
 no need to read register again here.

Regards,
Clark Wang


>=20
>  static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, @@ -900,6
> +921,13 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
>=20
>  	dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
>=20
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> +	if (i2c_imx->slave) {
> +		dev_err(&i2c_imx->adapter.dev, "Please not do operations
> of master mode in slave mode");
> +		return -EBUSY;
> +	}
> +#endif
> +
>  	result =3D pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
>  	if (result < 0)
>  		goto out;
> @@ -1048,11 +1076,166 @@ static u32 i2c_imx_func(struct i2c_adapter
> *adapter)
>  		| I2C_FUNC_SMBUS_READ_BLOCK_DATA;
>  }
>=20
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> +static int i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) {
> +	int temp;
> +
> +	/* Resume */
> +	temp =3D pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
> +	if (temp < 0) {
> +		dev_err(&i2c_imx->adapter.dev, "failed to resume i2c
> controller");
> +		return temp;
> +	}
> +
> +	/* Set slave addr. */
> +	imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx,
> IMX_I2C_IADR);
> +
> +	i2c_imx_reset_regs(i2c_imx);
> +
> +	/* Enable module */
> +	temp =3D i2c_imx->hwdata->i2cr_ien_opcode;
> +	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> +
> +	/* Enable interrupt from i2c module */
> +	temp |=3D I2CR_IIEN;
> +	imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> +
> +	/* Wait controller to be stable */
> +	usleep_range(50, 150);
> +	return 0;
> +}
> +
> +static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx) {
> +	unsigned int status, ctl;
> +	u8 value;
> +
> +	if (!i2c_imx->slave) {
> +		dev_err(&i2c_imx->adapter.dev, "cannot deal with slave
> irq,i2c_imx->slave is null");
> +		return IRQ_NONE;
> +	}
> +
> +	status =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> +	ctl =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
> +	if (status & I2SR_IAL) { /* Arbitration lost */
> +		i2c_imx_clr_al_bit(status, i2c_imx);
> +	} else if (status & I2SR_IAAS) { /* Addressed as a slave */
> +		if (status & I2SR_SRW) { /* Master wants to read from us*/
> +			dev_dbg(&i2c_imx->adapter.dev, "read requested");
> +			i2c_slave_event(i2c_imx->slave,
> I2C_SLAVE_READ_REQUESTED, &value);
> +
> +			/* Slave transmit */
> +			ctl |=3D I2CR_MTX;
> +			imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
> +
> +			/* Send data */
> +			imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
> +		} else { /* Master wants to write to us */
> +			dev_dbg(&i2c_imx->adapter.dev, "write requested");
> +			i2c_slave_event(i2c_imx->slave,
> 	I2C_SLAVE_WRITE_REQUESTED, &value);
> +
> +			/* Slave receive */
> +			ctl &=3D ~I2CR_MTX;
> +			imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
> +			/* Dummy read */
> +			imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
> +		}
> +	} else if (!(ctl & I2CR_MTX)) { /* Receive mode */
> +			if (status & I2SR_IBB) { /* No STOP signal detected */
> +				ctl &=3D ~I2CR_MTX;
> +				imx_i2c_write_reg(ctl, i2c_imx,
> IMX_I2C_I2CR);
> +
> +				value =3D imx_i2c_read_reg(i2c_imx,
> IMX_I2C_I2DR);
> +				i2c_slave_event(i2c_imx->slave,
> 	I2C_SLAVE_WRITE_RECEIVED, &value);
> +			} else { /* STOP signal is detected */
> +				dev_dbg(&i2c_imx->adapter.dev,
> +					"STOP signal detected");
> +				i2c_slave_event(i2c_imx->slave,
> I2C_SLAVE_STOP, &value);
> +			}
> +	} else if (!(status & I2SR_RXAK)) {	/* Transmit mode received
> ACK */
> +		ctl |=3D I2CR_MTX;
> +		imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
> +
> +		i2c_slave_event(i2c_imx->slave,
> 	I2C_SLAVE_READ_PROCESSED, &value);
> +
> +		imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
> +	} else { /* Transmit mode received NAK */
> +		ctl &=3D ~I2CR_MTX;
> +		imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
> +		imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
> +	}
> +	return IRQ_HANDLED;
> +}
> +
> +static int i2c_imx_reg_slave(struct i2c_client *client) {
> +	struct imx_i2c_struct *i2c_imx =3D i2c_get_adapdata(client->adapter);
> +	int ret;
> +	if (i2c_imx->slave)
> +		return -EBUSY;
> +
> +	i2c_imx->slave =3D client;
> +
> +	ret =3D i2c_imx_slave_init(i2c_imx);
> +	if (ret < 0)
> +		dev_err(&i2c_imx->adapter.dev, "failed to switch to slave
> mode");
> +
> +	return ret;
> +}
> +
> +static int i2c_imx_unreg_slave(struct i2c_client *client) {
> +	struct imx_i2c_struct *i2c_imx =3D i2c_get_adapdata(client->adapter);
> +	int ret;
> +
> +	if (!i2c_imx->slave)
> +		return -EINVAL;
> +
> +	/* Reset slave address. */
> +	imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
> +
> +	i2c_imx_reset_regs(i2c_imx);
> +
> +	i2c_imx->slave =3D NULL;
> +
> +	/* Suspend */
> +	ret =3D pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
> +	if (ret < 0)
> +		dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c
> controller");
> +
> +	return ret;
> +}
> +#endif
> +
>  static const struct i2c_algorithm i2c_imx_algo =3D {
>  	.master_xfer	=3D i2c_imx_xfer,
>  	.functionality	=3D i2c_imx_func,
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> +	.reg_slave	=3D i2c_imx_reg_slave,
> +	.unreg_slave	=3D i2c_imx_unreg_slave,
> +#endif
>  };
>=20
> +static irqreturn_t i2c_imx_isr(int irq, void *dev_id) {
> +	struct imx_i2c_struct *i2c_imx =3D dev_id;
> +	unsigned int status;
> +
> +	status =3D imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> +
> +	if (status & I2SR_IIF) {
> +		i2c_imx_clr_if_bit(status, i2c_imx);
> +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> +		if (i2c_imx->slave)
> +			return i2c_imx_slave_isr(i2c_imx);
> +#endif
> +		return i2c_imx_master_isr(i2c_imx);
> +	}
> +
> +	return IRQ_NONE;
> +}
> +
>  static int i2c_imx_probe(struct platform_device *pdev)  {
>  	struct imx_i2c_struct *i2c_imx;
> @@ -1148,10 +1331,7 @@ static int i2c_imx_probe(struct platform_device
> *pdev)
>  	clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
>  	i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
>=20
> -	/* Set up chip registers to defaults */
> -	imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
> -			i2c_imx, IMX_I2C_I2CR);
> -	imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
> IMX_I2C_I2SR);
> +	i2c_imx_reset_regs(i2c_imx);
>=20
>  	/* Init optional bus recovery function */
>  	ret =3D i2c_imx_init_recovery_info(i2c_imx, pdev);
> --
> 2.17.1