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From:   "james qian wang (Arm Technology China)" <james.qian.wang@arm.com>
To:     Mihail Atanassov <Mihail.Atanassov@arm.com>
CC:     nd <nd@arm.com>, Liviu Dudau <Liviu.Dudau@arm.com>,
        "airlied@linux.ie" <airlied@linux.ie>,
        Brian Starkey <Brian.Starkey@arm.com>,
        "maarten.lankhorst@linux.intel.com" 
        <maarten.lankhorst@linux.intel.com>,
        "Jonathan Chai (Arm Technology China)" <Jonathan.Chai@arm.com>,
        "Julien Yin (Arm Technology China)" <Julien.Yin@arm.com>,
        "Thomas Sun (Arm Technology China)" <thomas.Sun@arm.com>,
        "Lowry Li (Arm Technology China)" <Lowry.Li@arm.com>,
        "Tiannan Zhu (Arm Technology China)" <Tiannan.Zhu@arm.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>,
        Ben Davis <Ben.Davis@arm.com>,
        "Oscar Zhang (Arm Technology China)" <Oscar.Zhang@arm.com>,
        "Channing Chen (Arm Technology China)" <Channing.Chen@arm.com>
Subject: Re: [PATCH v2 2/2] drm/komeda: Enable new product D32 support
Thread-Topic: [PATCH v2 2/2] drm/komeda: Enable new product D32 support
Thread-Index: AQHVoEQnHODp0nh43k+zk6WDkpPTxKemwPIAgAFJKYA=
Date:   Tue, 3 Dec 2019 06:46:06 +0000
Message-ID: <20191203064559.GA17018@jamwan02-TSP300>
References: <20191121081717.29518-1-james.qian.wang@arm.com>
 <20191121081717.29518-3-james.qian.wang@arm.com>
 <15788924.1fOzIsmBsr@e123338-lin>
In-Reply-To: <15788924.1fOzIsmBsr@e123338-lin>
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On Mon, Dec 02, 2019 at 11:07:52AM +0000, Mihail Atanassov wrote:
> On Thursday, 21 November 2019 08:17:45 GMT james qian wang (Arm Technolog=
y China) wrote:
> > D32 is simple version of D71, the difference is:
> > - Only has one pipeline
> > - Drop the periph block and merge it to GCU
> >=20
> > v2: Rebase.
> >=20
> > Signed-off-by: James Qian Wang (Arm Technology China) <james.qian.wang@=
arm.com>
> > ---
> >  .../drm/arm/display/include/malidp_product.h  |  3 +-
> >  .../arm/display/komeda/d71/d71_component.c    |  2 +-
> >  .../gpu/drm/arm/display/komeda/d71/d71_dev.c  | 43 ++++++++++++-------
> >  .../gpu/drm/arm/display/komeda/d71/d71_regs.h | 13 ++++++
> >  .../gpu/drm/arm/display/komeda/komeda_drv.c   |  1 +
> >  5 files changed, 44 insertions(+), 18 deletions(-)
> >=20
> > diff --git a/drivers/gpu/drm/arm/display/include/malidp_product.h b/dri=
vers/gpu/drm/arm/display/include/malidp_product.h
> > index 96e2e4016250..dbd3d4765065 100644
> > --- a/drivers/gpu/drm/arm/display/include/malidp_product.h
> > +++ b/drivers/gpu/drm/arm/display/include/malidp_product.h
> > @@ -18,7 +18,8 @@
> >  #define MALIDP_CORE_ID_STATUS(__core_id)     (((__u32)(__core_id)) & 0=
xFF)
> > =20
> >  /* Mali-display product IDs */
> > -#define MALIDP_D71_PRODUCT_ID   0x0071
> > +#define MALIDP_D71_PRODUCT_ID	0x0071
> > +#define MALIDP_D32_PRODUCT_ID	0x0032
> > =20
> >  union komeda_config_id {
> >  	struct {
> > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/d=
rivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > index 6dadf4413ef3..c7f7e9c545c7 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c
> > @@ -1274,7 +1274,7 @@ static int d71_timing_ctrlr_init(struct d71_dev *=
d71,
> > =20
> >  	ctrlr =3D to_ctrlr(c);
> > =20
> > -	ctrlr->supports_dual_link =3D true;
> > +	ctrlr->supports_dual_link =3D d71->supports_dual_link;
> > =20
> >  	return 0;
> >  }
> > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c b/drivers=
/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > index 9b3bf353b6cc..2d429e310e5b 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_dev.c
> > @@ -371,23 +371,33 @@ static int d71_enum_resources(struct komeda_dev *=
mdev)
> >  		goto err_cleanup;
> >  	}
> > =20
> > -	/* probe PERIPH */
> > +	/* Only the legacy HW has the periph block, the newer merges the peri=
ph
> > +	 * into GCU
> > +	 */
> >  	value =3D malidp_read32(d71->periph_addr, BLK_BLOCK_INFO);
> > -	if (BLOCK_INFO_BLK_TYPE(value) !=3D D71_BLK_TYPE_PERIPH) {
> > -		DRM_ERROR("access blk periph but got blk: %d.\n",
> > -			  BLOCK_INFO_BLK_TYPE(value));
> > -		err =3D -EINVAL;
> > -		goto err_cleanup;
> > +	if (BLOCK_INFO_BLK_TYPE(value) !=3D D71_BLK_TYPE_PERIPH)
> > +		d71->periph_addr =3D NULL;
> > +
> > +	if (d71->periph_addr) {
> > +		/* probe PERIPHERAL in legacy HW */
> > +		value =3D malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID);
> > +
> > +		d71->max_line_size	=3D value & PERIPH_MAX_LINE_SIZE ? 4096 : 2048;
> > +		d71->max_vsize		=3D 4096;
> > +		d71->num_rich_layers	=3D value & PERIPH_NUM_RICH_LAYERS ? 2 : 1;
> > +		d71->supports_dual_link	=3D !!(value & PERIPH_SPLIT_EN);
> > +		d71->integrates_tbu	=3D !!(value & PERIPH_TBU_EN);
> > +	} else {
> > +		value =3D malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID0);
> > +		d71->max_line_size	=3D GCU_MAX_LINE_SIZE(value);
> > +		d71->max_vsize		=3D GCU_MAX_NUM_LINES(value);
> > +
> > +		value =3D malidp_read32(d71->gcu_addr, GCU_CONFIGURATION_ID1);
> > +		d71->num_rich_layers	=3D GCU_NUM_RICH_LAYERS(value);
> > +		d71->supports_dual_link	=3D GCU_DISPLAY_SPLIT_EN(value);
> > +		d71->integrates_tbu	=3D GCU_DISPLAY_TBU_EN(value);
> >  	}
> > =20
> > -	value =3D malidp_read32(d71->periph_addr, PERIPH_CONFIGURATION_ID);
> > -
> > -	d71->max_line_size	=3D value & PERIPH_MAX_LINE_SIZE ? 4096 : 2048;
> > -	d71->max_vsize		=3D 4096;
> > -	d71->num_rich_layers	=3D value & PERIPH_NUM_RICH_LAYERS ? 2 : 1;
> > -	d71->supports_dual_link	=3D value & PERIPH_SPLIT_EN ? true : false;
> > -	d71->integrates_tbu	=3D value & PERIPH_TBU_EN ? true : false;
> > -
> >  	for (i =3D 0; i < d71->num_pipelines; i++) {
> >  		pipe =3D komeda_pipeline_add(mdev, sizeof(struct d71_pipeline),
> >  					   &d71_pipeline_funcs);
> > @@ -415,7 +425,7 @@ static int d71_enum_resources(struct komeda_dev *md=
ev)
> >  	}
> > =20
> >  	/* loop the register blks and probe */
> > -	i =3D 2; /* exclude GCU and PERIPH */
> > +	i =3D 1; /* exclude GCU */
> >  	offset =3D D71_BLOCK_SIZE; /* skip GCU */
> >  	while (i < d71->num_blocks) {
> >  		blk_base =3D mdev->reg_base + (offset >> 2);
> > @@ -425,9 +435,9 @@ static int d71_enum_resources(struct komeda_dev *md=
ev)
> >  			err =3D d71_probe_block(d71, &blk, blk_base);
> >  			if (err)
> >  				goto err_cleanup;
> > -			i++;
> >  		}
> > =20
> > +		i++;
>=20
> This change doesn't make much sense if you want to count how many
> blocks are available, since you're now counting the reserved ones, too.

That's because for D32 num_blocks includes the reserved blocks.

> On the counting note, the prior code rides on the assumption the periph
> block is last in the map, and I don't see how you still handle not
> counting it in the D71 case.

Since D71 has one reserved block, and now we count reserved block.

So now no matter D32 or D71:
  num_blocks =3D n_valid_block + n_reserved_block + GCU.

Thanks
James
>=20
> >  		offset +=3D D71_BLOCK_SIZE;
> >  	}
> > =20
> > @@ -603,6 +613,7 @@ d71_identify(u32 __iomem *reg_base, struct komeda_c=
hip_info *chip)
> > =20
> >  	switch (product_id) {
> >  	case MALIDP_D71_PRODUCT_ID:
> > +	case MALIDP_D32_PRODUCT_ID:
> >  		funcs =3D &d71_chip_funcs;
> >  		break;
> >  	default:
> > diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h b/driver=
s/gpu/drm/arm/display/komeda/d71/d71_regs.h
> > index 1727dc993909..81de6a23e7f3 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
> > +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h
> > @@ -72,6 +72,19 @@
> >  #define GCU_CONTROL_MODE(x)	((x) & 0x7)
> >  #define GCU_CONTROL_SRST	BIT(16)
> > =20
> > +/* GCU_CONFIGURATION registers */
> > +#define GCU_CONFIGURATION_ID0	0x100
> > +#define GCU_CONFIGURATION_ID1	0x104
> > +
> > +/* GCU configuration */
> > +#define GCU_MAX_LINE_SIZE(x)	((x) & 0xFFFF)
> > +#define GCU_MAX_NUM_LINES(x)	((x) >> 16)
> > +#define GCU_NUM_RICH_LAYERS(x)	((x) & 0x7)
> > +#define GCU_NUM_PIPELINES(x)	(((x) >> 3) & 0x7)
> > +#define GCU_NUM_SCALERS(x)	(((x) >> 6) & 0x7)
> > +#define GCU_DISPLAY_SPLIT_EN(x)	(((x) >> 16) & 0x1)
> > +#define GCU_DISPLAY_TBU_EN(x)	(((x) >> 17) & 0x1)
> > +
> >  /* GCU opmode */
> >  #define INACTIVE_MODE		0
> >  #define TBU_CONNECT_MODE	1
> > diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c b/drivers/=
gpu/drm/arm/display/komeda/komeda_drv.c
> > index b7a1097c45c4..ad38bbc7431e 100644
> > --- a/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
> > +++ b/drivers/gpu/drm/arm/display/komeda/komeda_drv.c
> > @@ -125,6 +125,7 @@ static int komeda_platform_remove(struct platform_d=
evice *pdev)
> > =20
> >  static const struct of_device_id komeda_of_match[] =3D {
> >  	{ .compatible =3D "arm,mali-d71", .data =3D d71_identify, },
> > +	{ .compatible =3D "arm,mali-d32", .data =3D d71_identify, },
> >  	{},
> >  };
> > =20
> >=20
>=20
>=20
> --=20
> Mihail
>=20
>=20