Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp1011467ybl; Mon, 2 Dec 2019 23:33:01 -0800 (PST) X-Google-Smtp-Source: APXvYqwub0vaTAb9FuB/PrPsGrYIMjw9I/Kmnu5N+uGh/oSaFwLDKlmQSQuYJ654RtvbTAqbsn6R X-Received: by 2002:a54:4595:: with SMTP id z21mr2636762oib.136.1575358381765; Mon, 02 Dec 2019 23:33:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1575358381; cv=none; d=google.com; s=arc-20160816; b=oOZveBUHrOhRIavZBfpFDnommU+cJx6inK/lGd8l+Dy60iy9icannRlVCzJkOPxIdY epZ6/QD1SUZPhyi3AtW27Z8kv7iVxNPBn/SoMc7gQq/0M3DKC11Es2eJoQ/dHJhHnBbJ da0nerQLC1/9zC5swp5xhV4kjiRNhy+Sv065e7z6LXiV0iCdYVyYmMdyMr7SYy3rCzAJ lW9a/mK9GuWWmWp1OAyZgaTqyQBGLy4iDGqZvdYn7/ry2ZXbX8DyltW7E3NayWXX5MWr oW9lplfA7mK6J7EAva991YPZkVkECrLYY8+HaOZXpczB6S+WyZyw70PVW+FX21syjlzf 2KmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=MmZ+TQz4Vu0z3Vb6P9HOklg4kib0OW8FU78XaaPfN7M=; b=XtCRWLAFH19J5/cRLih21GJBxmFCcbeRRV5b5X1zA22xr0f+lbTRnGBm+HMUQOOMIN /5Mrgbcta8XES+sM7QT4GEJIi9eMG4LZsKzEQtpaoAkmcHh21phaMZutFNc5RVqh5B3C B6WgLHrVdwNQRKWErVPNglrH6j13jQn51FRFULYdjshDS73kBDONVFaqh6PdBFCX6njv wTZ7cEX70+GcJpoPC7dtw8l7qxu8cpALtBenk6wKCW63MHkx3bbnUjqFjV5bptSf2V8M lGB1EwRjflLN6Yb1p6X/Dik2N+IPI53w9HTHZJrJuOqkxFMgGnhKFHCwvC95cf8yyqVn QFGw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b15si929428oib.234.2019.12.02.23.32.50; Mon, 02 Dec 2019 23:33:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727484AbfLCHcW (ORCPT + 99 others); Tue, 3 Dec 2019 02:32:22 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:60339 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727451AbfLCHcU (ORCPT ); Tue, 3 Dec 2019 02:32:20 -0500 Received: from droid12-sz.software.amlogic (10.28.8.22) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server id 15.1.1591.10; Tue, 3 Dec 2019 15:32:44 +0800 From: Xingyu Chen To: Kevin Hilman , Neil Armstrong , Martin Blumenstingl CC: Xingyu Chen , Rob Herring , Jonathan Cameron , Jerome Brunet , Qianggui Song , Jianxin Pan , Jian Hu , , , , , Subject: [PATCH] arm64: dts: a1: add saradc controller Date: Tue, 3 Dec 2019 15:32:12 +0800 Message-ID: <1575358332-44866-1-git-send-email-xingyu.chen@amlogic.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.28.8.22] Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs, so we use the same compatible string. Signed-off-by: Xingyu Chen --- This patch is based on A1 clock patchset at [0]. [0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi index 7210ad0..cad1756 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -93,6 +93,21 @@ clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + saradc: adc@2c00 { + compatible = "amlogic,meson-g12a-saradc", + "amlogic,meson-saradc"; + reg = <0x0 0x2c00 0x0 0x48>; + #io-channel-cells = <1>; + interrupts = ; + clocks = <&xtal>, + <&clkc_periphs CLKID_SARADC>, + <&clkc_periphs CLKID_SARADC_CLK>, + <&clkc_periphs CLKID_SARADC_SEL>; + clock-names = "clkin", "core", "adc_clk", + "adc_sel"; + status = "disabled"; + }; }; gic: interrupt-controller@ff901000 { -- 2.7.4