Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Eric Auger <eric.auger@redhat.com>
To:     eric.auger.pro@gmail.com, eric.auger@redhat.com, maz@kernel.org,
        linux-kernel@vger.kernel.org, kvmarm@lists.cs.columbia.edu
Cc:     james.morse@arm.com, andrew.murray@arm.com, suzuki.poulose@arm.com,
        drjones@redhat.com
Subject: [RFC 2/3] KVM: arm64: pmu: Fix chained SW_INCR counters
Date:   Wed,  4 Dec 2019 21:44:25 +0100
Message-Id: <20191204204426.9628-3-eric.auger@redhat.com>
In-Reply-To: <20191204204426.9628-1-eric.auger@redhat.com>
References: <20191204204426.9628-1-eric.auger@redhat.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

At the moment a SW_INCR counter always overflows on 32-bit
boundary, independently on whether the n+1th counter is
programmed as CHAIN.

Check whether the SW_INCR counter is a 64b counter and if so,
implement the 64b logic.

Fixes: 80f393a23be6 ("KVM: arm/arm64: Support chained PMU counters")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
 virt/kvm/arm/pmu.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index c3f8b059881e..7ab477db2f75 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -491,6 +491,8 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, =
u64 val)
=20
 =09enable =3D __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
 =09for (i =3D 0; i < ARMV8_PMU_CYCLE_IDX; i++) {
+=09=09bool chained =3D test_bit(i >> 1, vcpu->arch.pmu.chained);
+
 =09=09if (!(val & BIT(i)))
 =09=09=09continue;
 =09=09type =3D __vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i)
@@ -500,8 +502,20 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu,=
 u64 val)
 =09=09=09reg =3D __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
 =09=09=09reg =3D lower_32_bits(reg);
 =09=09=09__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) =3D reg;
-=09=09=09if (!reg)
+=09=09=09if (reg) /* no overflow */
+=09=09=09=09continue;
+=09=09=09if (chained) {
+=09=09=09=09reg =3D __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i + 1) + 1;
+=09=09=09=09reg =3D lower_32_bits(reg);
+=09=09=09=09__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i + 1) =3D reg;
+=09=09=09=09if (reg)
+=09=09=09=09=09continue;
+=09=09=09=09/* mark an overflow on high counter */
+=09=09=09=09__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |=3D BIT(i + 1);
+=09=09=09} else {
+=09=09=09=09/* mark an overflow */
 =09=09=09=09__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |=3D BIT(i);
+=09=09=09}
 =09=09}
 =09}
 }
--=20
2.20.1