Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
IronPort-SDR: E3vxvqaQ5iuF6vk+Ig/HvTniuwf9/8Z7LhC7cdKDSpm0uFVy2fivotg4lVkFGRr47nNMEgVrIx
 4eQBNoIrDmgK/CbNH4hnmEgeVHLufXk3wY4wWO3Cb6GPf9/1cW10g5uycXE2lHfADvnvjOJpd4
 PsLXYk70HN6VInviyHhpH3Dn/ET/YRUiaXmAKxBT/1LXQoxBwYTPX1YUq2hDW7A59yVpVHTB8p
 eATkxjO7nGsAtlxi1pRV2csWlSiEHnmpamxbb/46Bzfl+5KlUMpl0GAQdKcQjjJxW/vxBNjmJ/
 VN0=
From:   Anup Patel <Anup.Patel@wdc.com>
To:     Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>
CC:     Atish Patra <Atish.Patra@wdc.com>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        Christoph Hellwig <hch@lst.de>,
        Anup Patel <anup@brainfault.org>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Anup Patel <Anup.Patel@wdc.com>
Subject: [PATCH] RISC-V: Add debug defconfigs
Thread-Topic: [PATCH] RISC-V: Add debug defconfigs
Thread-Index: AQHVqwbRBzOF14qKU02iX5oJLiweww==
Date:   Thu, 5 Dec 2019 00:56:25 +0000
Message-ID: <20191205005601.1559-1-anup.patel@wdc.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-messagesentrepresentingtype: 1
x-mailer: git-send-email 2.17.1
x-originating-ip: [199.255.44.250]
x-ms-publictraffictype: Email
x-ms-office365-filtering-ht: Tenant
x-ms-office365-filtering-correlation-id: e53812ec-9f68-4d1f-58d1-08d7791df3f4
x-ms-traffictypediagnostic: MN2PR04MB6910:
x-ms-exchange-transport-forked: True
x-microsoft-antispam-prvs: <MN2PR04MB6910D39AD71D4A020FECF7878D5C0@MN2PR04MB6910.namprd04.prod.outlook.com>
wdcipoutbound: EOP-TRUE
x-ms-oob-tlc-oobclassifiers: OLM:5236;
x-forefront-prvs: 02426D11FE
x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(4636009)(39860400002)(366004)(136003)(396003)(346002)(376002)(189003)(199004)(50226002)(6116002)(66446008)(99286004)(6512007)(6436002)(81156014)(81166006)(36756003)(8676002)(6506007)(66946007)(66476007)(478600001)(64756008)(52116002)(6486002)(2616005)(86362001)(25786009)(8936002)(44832011)(3846002)(66556008)(54906003)(316002)(110136005)(102836004)(14454004)(2906002)(2171002)(26005)(4326008)(5660300002)(305945005)(71200400001)(71190400001)(1076003)(7736002)(186003);DIR:OUT;SFP:1102;SCL:1;SRVR:MN2PR04MB6910;H:MN2PR04MB6061.namprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1;
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam: BCL:0;
x-microsoft-antispam-message-info: P/PXPKXuxt8Cw4hHtm7GZzbZicAFN7K82z1rTNuzgvKd4fc5qxx7um52itvMt3cTiwBxbHovsCruW9ab2IsepngLy2mkgDDNqja4+Zql5P3K/4FRoUbG1cIivaVzmt/JzjmVBM4ar+atorTc5126nMsWCS0qn5BQt7cLgwChHDUpe7dF4eKENkEqJMNAY3pWQc6XKArEj1ZV72Hp2oD0bfpxxVUFXPNboovjXd3p7fubRefCftQvggZPuOSc4FwhgsVgoGfdvXa/WhVFxJlEVoneXXj3DcB/I8JuTmdpnXCIqKvSX6vnVSzxPMM/A5drDN+AmgvmayXtTMaipCLF0dPoeqN4IHOA1TKn+F4qdu5D2kpvCjvtElmPM/WCYNW/FWpSn+w4z+wsNLdqyvwirSrE0x/10nhSo7izYVbHi41yHoMho7rV65CwFU/76gX4
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: wdc.com
X-MS-Exchange-CrossTenant-Network-Message-Id: e53812ec-9f68-4d1f-58d1-08d7791df3f4
X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Dec 2019 00:56:25.2582
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: sbpIfddytRlWNsTi/kcaev9VOn9RkgUqGvE/pH76uppPMB/425tHyrjmBHsa4+734kRR/g2DYkRHJ6JdW4LgHA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6910
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Various Linux kernel DEBUG options have big performance impact
so these should not be enabled in RISC-V normal defconfigs.

Instead we should have separate RISC-V debug defconfigs having
these DEBUG options enabled. This way Linux RISC-V can build both
non-debug and debug kernels separately.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 .../configs/{defconfig =3D> debug_defconfig}    |  0
 arch/riscv/configs/defconfig                  | 23 -------------------
 .../{rv32_defconfig =3D> rv32_debug_defconfig}  |  0
 arch/riscv/configs/rv32_defconfig             | 23 -------------------
 4 files changed, 46 deletions(-)
 copy arch/riscv/configs/{defconfig =3D> debug_defconfig} (100%)
 copy arch/riscv/configs/{rv32_defconfig =3D> rv32_debug_defconfig} (100%)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/debug_defcon=
fig
similarity index 100%
copy from arch/riscv/configs/defconfig
copy to arch/riscv/configs/debug_defconfig
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index e2ff95cb3390..f0710d8f50cc 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -101,27 +101,4 @@ CONFIG_CRYPTO_USER_API_HASH=3Dy
 CONFIG_CRYPTO_DEV_VIRTIO=3Dy
 CONFIG_PRINTK_TIME=3Dy
 CONFIG_DEBUG_FS=3Dy
-CONFIG_DEBUG_PAGEALLOC=3Dy
-CONFIG_DEBUG_VM=3Dy
-CONFIG_DEBUG_VM_PGFLAGS=3Dy
-CONFIG_DEBUG_MEMORY_INIT=3Dy
-CONFIG_DEBUG_PER_CPU_MAPS=3Dy
-CONFIG_SOFTLOCKUP_DETECTOR=3Dy
-CONFIG_WQ_WATCHDOG=3Dy
-CONFIG_SCHED_STACK_END_CHECK=3Dy
-CONFIG_DEBUG_TIMEKEEPING=3Dy
-CONFIG_DEBUG_RT_MUTEXES=3Dy
-CONFIG_DEBUG_SPINLOCK=3Dy
-CONFIG_DEBUG_MUTEXES=3Dy
-CONFIG_DEBUG_RWSEMS=3Dy
-CONFIG_DEBUG_ATOMIC_SLEEP=3Dy
-CONFIG_STACKTRACE=3Dy
-CONFIG_DEBUG_LIST=3Dy
-CONFIG_DEBUG_PLIST=3Dy
-CONFIG_DEBUG_SG=3Dy
 # CONFIG_RCU_TRACE is not set
-CONFIG_RCU_EQS_DEBUG=3Dy
-CONFIG_DEBUG_BLOCK_EXT_DEVT=3Dy
-# CONFIG_FTRACE is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_MEMTEST=3Dy
diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_de=
bug_defconfig
similarity index 100%
copy from arch/riscv/configs/rv32_defconfig
copy to arch/riscv/configs/rv32_debug_defconfig
diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_de=
fconfig
index eb519407c841..bdec58e6c5f7 100644
--- a/arch/riscv/configs/rv32_defconfig
+++ b/arch/riscv/configs/rv32_defconfig
@@ -98,27 +98,4 @@ CONFIG_CRYPTO_USER_API_HASH=3Dy
 CONFIG_CRYPTO_DEV_VIRTIO=3Dy
 CONFIG_PRINTK_TIME=3Dy
 CONFIG_DEBUG_FS=3Dy
-CONFIG_DEBUG_PAGEALLOC=3Dy
-CONFIG_DEBUG_VM=3Dy
-CONFIG_DEBUG_VM_PGFLAGS=3Dy
-CONFIG_DEBUG_MEMORY_INIT=3Dy
-CONFIG_DEBUG_PER_CPU_MAPS=3Dy
-CONFIG_SOFTLOCKUP_DETECTOR=3Dy
-CONFIG_WQ_WATCHDOG=3Dy
-CONFIG_SCHED_STACK_END_CHECK=3Dy
-CONFIG_DEBUG_TIMEKEEPING=3Dy
-CONFIG_DEBUG_RT_MUTEXES=3Dy
-CONFIG_DEBUG_SPINLOCK=3Dy
-CONFIG_DEBUG_MUTEXES=3Dy
-CONFIG_DEBUG_RWSEMS=3Dy
-CONFIG_DEBUG_ATOMIC_SLEEP=3Dy
-CONFIG_STACKTRACE=3Dy
-CONFIG_DEBUG_LIST=3Dy
-CONFIG_DEBUG_PLIST=3Dy
-CONFIG_DEBUG_SG=3Dy
 # CONFIG_RCU_TRACE is not set
-CONFIG_RCU_EQS_DEBUG=3Dy
-CONFIG_DEBUG_BLOCK_EXT_DEVT=3Dy
-# CONFIG_FTRACE is not set
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_MEMTEST=3Dy
--=20
2.17.1