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Subject: Re: [PATCH v1 1/2] clk: intel: Add CGU clock driver for a new SoC
To:     Andy Shevchenko <andriy.shevchenko@intel.com>
Cc:     mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        robhkernel.org@smile.fi.intel.com, mark.rutland@arm.com,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
        qi-ming.wu@intel.com, yixin.zhu@linux.intel.com,
        cheol.yong.kim@intel.com, rahul.tanwar@intel.com
References: <cover.1566975410.git.rahul.tanwar@linux.intel.com>
 <6a3c26bc6e25d883686287883528dbde30725922.1566975410.git.rahul.tanwar@linux.intel.com>
 <20190828150951.GS2680@smile.fi.intel.com>
 <e4a1fd0a-b179-92dd-fb81-22d9d7465a33@linux.intel.com>
 <20190902122030.GE2680@smile.fi.intel.com>
 <20190902122454.GF2680@smile.fi.intel.com>
From:   "Tanwar, Rahul" <rahul.tanwar@linux.intel.com>
Message-ID: <db9b8978-b9ae-d1bf-2477-78a99b82367a@linux.intel.com>
Date:   Fri, 6 Dec 2019 12:39:51 +0800
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Hi Andy,

On 2/9/2019 8:24 PM, Andy Shevchenko wrote:
> On Mon, Sep 02, 2019 at 03:20:30PM +0300, Andy Shevchenko wrote:
>> On Mon, Sep 02, 2019 at 03:43:13PM +0800, Tanwar, Rahul wrote:
>>> On 28/8/2019 11:09 PM, Andy Shevchenko wrote:
>>>> On Wed, Aug 28, 2019 at 03:00:17PM +0800, Rahul Tanwar wrote:
>>>> Does val == 0 follows the table, i.e. makes div == 1?
>>> 0 val means output clock is ref clock i.e. div ==1. Agree that adding
>>> .val = 0, .div =1 entry will make it more clear & complete.
>>>
>>>>> +	{ .val = 0, .div = 1 },
>>>>> +	{ .val = 1, .div = 2 },
>>>>> +	{ .val = 2, .div = 3 },
>> 1
>>
>>>>> +	{ .val = 3, .div = 4 },
>>>>> +	{ .val = 4, .div = 5 },
>>>>> +	{ .val = 5, .div = 6 },
>> 1
>>
>>>>> +	{ .val = 6, .div = 8 },
>>>>> +	{ .val = 7, .div = 10 },
>>>>> +	{ .val = 8, .div = 12 },
>> 2
>>
>>>>> +	{ .val = 9, .div = 16 },
>>>>> +	{ .val = 10, .div = 20 },
>>>>> +	{ .val = 11, .div = 24 },
>> 4
>>
>>>>> +	{ .val = 12, .div = 32 },
>>>>> +	{ .val = 13, .div = 40 },
>>>>> +	{ .val = 14, .div = 48 },
>> 8
>>
>>>>> +	{ .val = 15, .div = 64 },
>> 16
>>
>>
>> So, now we see the pattern:
>>
>> 	div = val < 3 ? (val + 1) : (1 << ((val - 3) / 3));
> It's not complete, but I think you got the idea.
>
>> So, can we eliminate table?

In the desperation to eliminate table, below is what i can come up with:

        struct clk_div_table div_table[16];
        int i, j;

        for (i = 0; i < 16; i++)
                div_table[i].val = i;

        for (i = 0, j=0; i < 16; i+=3, j++) {
                div_table[i].div = (i == 0) ? (1 << j) : (1 << (j + 1));
                if (i == 15)
                        break;

                div_table[i + 1].div = (i == 0) ? ((1 << j) + 1) :
                                        (1 << (j + 1)) + (1 << (j - 1));
                div_table[i + 2].div = (3 << j);
        }

To me, table still looks a better approach. Also, table is more extendable &
consistent w.r.t. clk framework & other referenced clk drivers.

Whats your opinion ?

Regards,
Rahul