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Subject: Re: [PATCH v3 06/15] clk: tegra: Remove tegra_pmc_clk_init along with
 clk ids
To:     Sowjanya Komatineni <skomatineni@nvidia.com>,
        thierry.reding@gmail.com, jonathanh@nvidia.com,
        mperttunen@nvidia.com, gregkh@linuxfoundation.org,
        sboyd@kernel.org, tglx@linutronix.de, robh+dt@kernel.org,
        mark.rutland@arm.com
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        Jisheng.Zhang@synaptics.com, krzk@kernel.org, arnd@arndb.de,
        spujar@nvidia.com, josephl@nvidia.com, vidyas@nvidia.com,
        daniel.lezcano@linaro.org, mmaddireddy@nvidia.com,
        markz@nvidia.com, devicetree@vger.kernel.org,
        linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org, lgirdwood@gmail.com,
        broonie@kernel.org, perex@perex.cz, tiwai@suse.com,
        alexios.zavras@intel.com, alsa-devel@alsa-project.org
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From:   Dmitry Osipenko <digetx@gmail.com>
Message-ID: <f8188f0d-ec7e-7d4a-f977-16273b594838@gmail.com>
Date:   Sun, 8 Dec 2019 02:24:52 +0300
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07.12.2019 22:35, Sowjanya Komatineni пишет:
> 
> On 12/7/19 7:04 AM, Dmitry Osipenko wrote:
>> 07.12.2019 17:43, Dmitry Osipenko пишет:
>>> 07.12.2019 17:33, Dmitry Osipenko пишет:
>>>> 06.12.2019 05:48, Sowjanya Komatineni пишет:
>>>>> Current Tegra clock driver registers PMC clocks clk_out_1, clk_out_2,
>>>>> clk_out_3 and blink output in tegra_pmc_init() which does direct Tegra
>>>>> PMC access during clk_ops and these PMC register read and write access
>>>>> will not happen when PMC is in secure mode.
>>>>>
>>>>> Any direct PMC register access from non-secure world will not go
>>>>> through and all the PMC clocks and blink control are done in Tegra PMC
>>>>> driver with PMC as clock provider.
>>>>>
>>>>> This patch removes tegra_pmc_clk_init along with corresponding clk ids
>>>>> from Tegra clock driver.
>>>>>
>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>> ---
>>>> [snip]
>>>>
>>>>> @@ -1230,9 +1222,6 @@ static struct tegra_clk_init_table
>>>>> init_table[] __initdata = {
>>>>>       { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
>>>>>       { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
>>>>>       { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
>>>> Perhaps these clocks do not need to be always-enabled?
>>>>
>>>> [snip]
>>>>
>>> Also, EXTERN1 parent configuration should be moved to the audio
>>> driver/device-tree as well.
>> Ah, I missed that it's done in the patch #10.
> Yes its done in Patch#10
>>
>>> Maybe it even makes sense to move the whole configuration, including
>>> PLLA. I don't see why clk driver need to do something for the audio
>>> driver.
> 
> Current ASoC driver already takes care of PLLA rate and enables.
> 
> So PLLA init can be removed from clock driver too. I didn't went through
> complete audio driver to be confident to remove this.
> 
> But PLLA is needed for i2s clock also and currently I2S driver takes
> care of only I2S clock rate using PLLA as parent set by clock driver and
> clock driver enables PLLA earlier to have it ready by the time both I2S
> driver and ASoC driver .
I2S could use assigned-clocks, but probably it's not really necessary
and predefined configuration in the clk driver is good enough.

At least PLLA doesn't need to be always-enabled since audio drivers
enable it when necessary.