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[209.132.180.67]) by mx.google.com with ESMTP id i12si10654286oik.171.2019.12.08.12.58.01; Sun, 08 Dec 2019 12:58:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726687AbfLHUzX (ORCPT + 99 others); Sun, 8 Dec 2019 15:55:23 -0500 Received: from relay7-d.mail.gandi.net ([217.70.183.200]:43707 "EHLO relay7-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726513AbfLHUzW (ORCPT ); Sun, 8 Dec 2019 15:55:22 -0500 X-Originating-IP: 88.190.179.123 Received: from localhost (unknown [88.190.179.123]) (Authenticated sender: repk@triplefau.lt) by relay7-d.mail.gandi.net (Postfix) with ESMTPSA id 56DA720005; Sun, 8 Dec 2019 20:55:18 +0000 (UTC) From: Remi Pommarel To: Neil Armstrong , Jerome Brunet , Kevin Hilman , Yue Wang Cc: Michael Turquette , Stephen Boyd , Lorenzo Pieralisi , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Remi Pommarel Subject: [PATCH 1/2] clk: meson: axg: add pcie pll cml gating Date: Sun, 8 Dec 2019 22:03:19 +0100 Message-Id: <20191208210320.15539-2-repk@triplefau.lt> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191208210320.15539-1-repk@triplefau.lt> References: <20191208210320.15539-1-repk@triplefau.lt> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCIE_PLL_CML_ENABLE is used to enable or disable pcie clock PAD output reliably on AXG platforms. Signed-off-by: Remi Pommarel --- drivers/clk/meson/axg.c | 3 +++ drivers/clk/meson/axg.h | 2 +- include/dt-bindings/clock/axg-clkc.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 13fc0006f63d..ac9ab7f75ee8 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1142,6 +1142,7 @@ static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25); static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30); static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29); +static MESON_GATE(axg_pcie_pll_cml_enable, HHI_MIPI_CNTL0, 26); /* Always On (AO) domain gates */ @@ -1246,6 +1247,7 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = { [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw, [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw, [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw, + [CLKID_PCIE_PLL_CML_ENABLE] = &axg_pcie_pll_cml_enable.hw, [NR_CLKS] = NULL, }, .num = NR_CLKS, @@ -1341,6 +1343,7 @@ static struct clk_regmap *const axg_clk_regmaps[] = { &axg_hifi_pll_dco, &axg_pcie_pll_dco, &axg_pcie_pll_od, + &axg_pcie_pll_cml_enable, }; static const struct meson_eeclkc_data axg_clkc_data = { diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h index 0431dabac629..d65670d6c607 100644 --- a/drivers/clk/meson/axg.h +++ b/drivers/clk/meson/axg.h @@ -140,7 +140,7 @@ #define CLKID_PCIE_PLL_DCO 89 #define CLKID_PCIE_PLL_OD 90 -#define NR_CLKS 91 +#define NR_CLKS 92 /* include the CLKIDs that have been made part of the DT binding */ #include diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index fd1f938c38d1..218a05ff508d 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -72,5 +72,6 @@ #define CLKID_PCIE_CML_EN1 80 #define CLKID_MIPI_ENABLE 81 #define CLKID_GEN_CLK 84 +#define CLKID_PCIE_PLL_CML_ENABLE 91 #endif /* __AXG_CLKC_H */ -- 2.24.0