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To:     Qais Yousef <qais.yousef@arm.com>
Subject: Re: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity  for managed interrupt
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Date:   Mon, 09 Dec 2019 15:55:03 +0000
From:   Marc Zyngier <maz@kernel.org>
Cc:     Hannes Reinecke <hare@suse.de>, John Garry <john.garry@huawei.com>,
        Ming Lei <ming.lei@redhat.com>, <tglx@linutronix.de>,
        <chenxiang66@hisilicon.com>, <bigeasy@linutronix.de>,
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        <mingo@redhat.com>
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On 2019-12-09 15:49, Qais Yousef wrote:
> On 12/09/19 15:17, Marc Zyngier wrote:
>> On 2019-12-09 15:09, Hannes Reinecke wrote:
>>
>> [slight digression]
>>
>> > My idea here is slightly different: can't we leverage SMT?
>> > Most modern CPUs do SMT (I guess even ARM does it nowadays)
>> > (Yes, I know about spectre and things. We're talking performance 
>> here
>> > :-)
>>
>> I only know two of those: Cavium TX2 and ARM Neoverse-E1.
>
> There's the Cortex-A65 too.

Which is the exact same core as E1 (but don't tell anyone... ;-).

         M.
-- 
Jazz is not dead. It just smells funny...