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[71.197.186.152]) by smtp.gmail.com with ESMTPSA id g19sm504235pfh.134.2019.12.09.14.56.33 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Dec 2019 14:56:33 -0800 (PST) From: Kevin Hilman To: Xingyu Chen , Neil Armstrong , Martin Blumenstingl Cc: Xingyu Chen , Rob Herring , Jonathan Cameron , Jerome Brunet , Qianggui Song , Jianxin Pan , Jian Hu , linux-iio@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH] arm64: dts: a1: add saradc controller In-Reply-To: <1575358332-44866-1-git-send-email-xingyu.chen@amlogic.com> References: <1575358332-44866-1-git-send-email-xingyu.chen@amlogic.com> Date: Mon, 09 Dec 2019 14:56:32 -0800 Message-ID: <7hpngxqfa7.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Xingyu Chen writes: > The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs, > so we use the same compatible string. > > Signed-off-by: Xingyu Chen > > --- > This patch is based on A1 clock patchset at [0]. > > [0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com > --- > arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > index 7210ad0..cad1756 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi > @@ -93,6 +93,21 @@ > clock-names = "xtal", "pclk", "baud"; > status = "disabled"; > }; > + > + saradc: adc@2c00 { > + compatible = "amlogic,meson-g12a-saradc", > + "amlogic,meson-saradc"; > + reg = <0x0 0x2c00 0x0 0x48>; Why 0x48 here? AXG uses 0x38 and you're not adding any more registers to this driver. Kevin