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([2001:b07:6468:f312:e9bb:92e9:fcc3:7ba9]) by smtp.gmail.com with ESMTPSA id r6sm2437618wrq.92.2019.12.10.01.18.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Dec 2019 01:18:53 -0800 (PST) Subject: Re: [PATCH v2] KVM: x86: use CPUID to locate host page table reserved bits To: "Huang, Kai" , "thomas.lendacky@amd.com" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" Cc: "Christopherson, Sean J" , "stable@vger.kernel.org" References: <1575474037-7903-1-git-send-email-pbonzini@redhat.com> <8f7e3e87-15dc-2269-f5ee-c3155f91983c@amd.com> <2f3d8c9b146301183b891d8a441aa4a5c33b4c9d.camel@intel.com> From: Paolo Bonzini Message-ID: Date: Tue, 10 Dec 2019 10:18:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <2f3d8c9b146301183b891d8a441aa4a5c33b4c9d.camel@intel.com> Content-Language: en-US X-MC-Unique: -BG5azkIP3S49yX7a7v6PA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/12/19 04:53, Huang, Kai wrote: > Right. Alghouth both MKTME and SME/SEV reduce physical bits, but they treat > those reduced bits differently: MKTME treats those as keyID thus they can be > set, but SME/SEV treats those as reserved bits so you cannot set any of them. > > Maybe the naming of shadow_phys_bits is a little bit confusing here. The purpose > of it was to determine first reserved bits, but not actual physical address bits > . Therefore for MKTME it should include the keyID bits, but for SME/SEV it > should not. Not just the first reserved bit, but _some_ reserved bit such that all consecutive bits up to bit 51 are reserved. Paolo