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[209.132.180.67]) by mx.google.com with ESMTP id n2si44664otk.177.2019.12.10.16.31.11; Tue, 10 Dec 2019 16:31:23 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@aj.id.au header.s=fm1 header.b="ZgyUrBP/"; dkim=pass header.i=@messagingengine.com header.s=fm1 header.b=nvtlJ7x+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727114AbfLKAaa (ORCPT + 99 others); Tue, 10 Dec 2019 19:30:30 -0500 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:40251 "EHLO out4-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726771AbfLKAaa (ORCPT ); Tue, 10 Dec 2019 19:30:30 -0500 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 4452222611; Tue, 10 Dec 2019 19:30:29 -0500 (EST) Received: from imap2 ([10.202.2.52]) by compute4.internal (MEProxy); Tue, 10 Dec 2019 19:30:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h= mime-version:message-id:in-reply-to:references:date:from:to:cc :subject:content-type; s=fm1; bh=rLVrKFn1e9XoYm6vW5UZkkz+J1OlgvA Bn/hbvdEf6xA=; b=ZgyUrBP/dSEnxvkY8KRknAovC8fWiLWxAPri0JddEv2wpbt 8XkYPg5v8z5UXGDEisPsuEoguh3mRqAVQHXpbATiKvYx25KzbxCfIrGnwp+vCsDy gEZaIh707rLLt39hQzqkgQXTuikj9yuLv0PIDu71XYhcUZCJr+mv19PYl4pbbA0W zOrfA4k802Vw4UlRG4vWFViv5Db2wmRbTbecFUAtO0zwZh6ERsKImcwmISBslW85 /UzAWLmiW+Sv7r7mX7AKXZXViKvEetc89firz44/ciq67vejDeNv7SknrXU0xbHZ 3bciUhf0IenO5HEihvu+bHV5GUq3Go2THcDbMIQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-proxy :x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s=fm1; bh=rLVrKF n1e9XoYm6vW5UZkkz+J1OlgvABn/hbvdEf6xA=; b=nvtlJ7x+wA/3kzg2Vj2QeI 4ZdRaAYkzOJ8nFpvZTNBFjG+jumNaaEOGCysWN+TuheV50JcVW/pnbugHFaR/3FK LrWetfs88GNVS4RrJxiZ9N5SHZuwYeqJ6Yzkn5qd80nmjUuHwz1ZEPKFnN1fg+3s 7NSWdMyGS2b4SGwfiaa1bQlUY7gICDxPlVxYfjEIvWSjqf1fZG8iLCbAx+8aIs2y 83iqIVwJ3V56POQMCB5mWCkATs5SZNhwvZicRviaQxo+GjGFY3c5Qg2GY6LTpPGT v9X1fCOZLiYPG9BpU2JvGw1WvsDnLZnRcxahVBs8IO6ZCXdOl/USgxKElmqcSXjA == X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrudelgedgudeiucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepofgfggfkjghffffhvffutgesthdtredtreertdenucfhrhhomhepfdetnhgu rhgvficulfgvfhhfvghrhidfuceorghnughrvgifsegrjhdrihgurdgruheqnecurfgrrh grmhepmhgrihhlfhhrohhmpegrnhgurhgvfiesrghjrdhiugdrrghunecuvehluhhsthgv rhfuihiivgeptd X-ME-Proxy: Received: by mailuser.nyi.internal (Postfix, from userid 501) id 4A7B7E00A2; Tue, 10 Dec 2019 19:30:28 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.7-679-g1f7ccac-fmstable-20191210v1 Mime-Version: 1.0 Message-Id: <40bf8eb4-2998-43fd-af61-c9063b09ced9@www.fastmail.com> In-Reply-To: <1575566112-11658-3-git-send-email-eajames@linux.ibm.com> References: <1575566112-11658-1-git-send-email-eajames@linux.ibm.com> <1575566112-11658-3-git-send-email-eajames@linux.ibm.com> Date: Wed, 11 Dec 2019 11:02:08 +1030 From: "Andrew Jeffery" To: "Eddie James" , linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, "Jason Cooper" , linux-aspeed@lists.ozlabs.org, "Marc Zyngier" , "Rob Herring" , tglx@linutronix.de, mark.rutland@arm.com, "Joel Stanley" Subject: Re: [PATCH v2 02/12] irqchip: Add Aspeed SCU interrupt controller Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 6 Dec 2019, at 03:45, Eddie James wrote: > The Aspeed SOCs provide some interrupts through the System Control > Unit registers. Add an interrupt controller that provides these > interrupts to the system. > > Signed-off-by: Eddie James Reviewed-by: Andrew Jeffery