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[209.132.180.67]) by mx.google.com with ESMTP id i205si519308oih.257.2019.12.10.21.48.23; Tue, 10 Dec 2019 21:48:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nifty.com header.s=dec2015msa header.b="abIzf/VH"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726686AbfLKFrd (ORCPT + 99 others); Wed, 11 Dec 2019 00:47:33 -0500 Received: from conuserg-10.nifty.com ([210.131.2.77]:23023 "EHLO conuserg-10.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725800AbfLKFrd (ORCPT ); Wed, 11 Dec 2019 00:47:33 -0500 Received: from localhost.localdomain (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-10.nifty.com with ESMTP id xBB5jdVa019523; Wed, 11 Dec 2019 14:45:40 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-10.nifty.com xBB5jdVa019523 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1576043141; bh=UxDx8RnuQhkTN8+zyVJvCjCQ3hY035WRmN5rhX+qiCg=; h=From:To:Cc:Subject:Date:From; b=abIzf/VHWf80xkCNM9Nq9l7bCTZhTmzvAGgpyGNxWkKxeNhSUY0HzAoJS1K5AHGZx qcghRfQPNCejAohtVrKvGe/1q2hkoB7P1vRWONc2sa3mkdinujSyiHWkpZaoDcHVT2 zLPKf8piCsaFj9Z/2bobrErHtgQrZf7eTZhphVaG76AjykCd1sXuqDV4q+Y4tejqhZ wZfufdLfCb6ZEkfRpHSeyvPdwg4bWncJdnoa0uyZE0hiubTf/osHL2jjna/WnDaNk1 nEwqKSCGynuEPXml7xxwpm/HF52oewbK7/qwron40H4rYnyHkUjYBlZuDcRXj5UonQ V6RaKNL1cLNvQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: linux-mtd@lists.infradead.org Cc: Dinh Nguyen , Marek Vasut , Ley Foon Tan , Miquel Raynal , devicetree@vger.kernel.org, Rob Herring , Philipp Zabel , Masahiro Yamada , Mark Rutland , Richard Weinberger , Vignesh Raghavendra , linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-binding: mtd: denali_dt: document reset property Date: Wed, 11 Dec 2019 14:45:37 +0900 Message-Id: <20191211054538.8283-1-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.17.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to the Denali NAND Flash Memory Controller User's Guide, this IP has two reset signals. rst_n: reset most of FFs in the controller core reg_rst_n: reset all FFs in the register interface, and in the initialization sequencer This commit specifies those reset signals. It is possible to control them separately from the IP point of view although they might be often tied up together in actual SoC integration. At least for the upstream platforms, Altera/Intel SOCFPGA and Socionext UniPhier, the reset controller seems to provide only 1-bit control for the NAND controller. If it is the case, the resets property should reference to the same phandles for "nand" and "reg" resets, like this: resets = <&nand_rst>, <&nand_rst>; reset-names = "nand", "reg"; Signed-off-by: Masahiro Yamada --- Changes in v2: - Split into two patches Documentation/devicetree/bindings/mtd/denali-nand.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt index b32aed1db46d..98916a84bbf6 100644 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt @@ -14,6 +14,11 @@ Required properties: interface clock, and the ECC circuit clock. - clock-names: should contain "nand", "nand_x", "ecc" +Optional properties: + - resets: may contain phandles to the controller core reset, the register + reset + - reset-names: may contain "nand", "reg" + Sub-nodes: Sub-nodes represent available NAND chips. @@ -46,6 +51,8 @@ nand: nand@ff900000 { reg-names = "nand_data", "denali_reg"; clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; clock-names = "nand", "nand_x", "ecc"; + resets = <&nand_rst>, <&nand_reg_rst>; + reset-names = "nand", "reg"; interrupts = <0 144 4>; nand@0 { -- 2.17.1