Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp979610ybl; Thu, 12 Dec 2019 07:54:04 -0800 (PST) X-Google-Smtp-Source: APXvYqw1w+ACjwj0+1wVpfl83A2ccauZm2DI7aZZ2u/LSrlqhVWCbnv1DeARQsMHLNHFBOvlCE+t X-Received: by 2002:a9d:70cb:: with SMTP id w11mr9024160otj.157.1576166044702; Thu, 12 Dec 2019 07:54:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576166044; cv=none; d=google.com; s=arc-20160816; b=nfJz7MktQETSsSOzdUVVTStZzYq/8xQHbdHyNcnvv3p2llGW0XNud/HJaE2FvnaI0C ViMlNjWMmikyjb9HB67AbVRWTvoGaeIhF9tzkYYoSEzjzYsNiYOlnOa4brf02jGIq6TR J57sKy8hcNXcbcsNoDEgVM9OMWLrgwNOM6unCBzGy24qY+SCjMvPfiJLLnoL/gYUiMAs CvVPZPWirLlAKyJVN4Lo4LD5DtOyJDFf0USehnNgY/661bpHBGnTVBEw3uZutOhEOO7W BSrdj6zGkoffFcXh2d7wLq4s5N9E/KJbrrQmPgvBG+ECDuqd5YzBT9Cmbmk+AVmvNF0K V9XQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:user-agent:in-reply-to :content-transfer-encoding:content-disposition:mime-version :references:message-id:subject:cc:to:from:date:dkim-signature; bh=ppVt/c6SNGbxwMT06FmYWiQkL8ReCtZAObgQLli/bGc=; b=TM8eaNQWqHStCM2GsRc/rVNy52gHNxmwaG0b+1Z08K9WEGxf7hODGtJIQmOxceT0GQ vydgd5HLhPyZLah1YqF9CiI7e2fkTpvoamMe37Kmnky4y3g/6IklFWm3X9CFxwWfIwpU mkvb/vuEdECJk6dPGgaG0VedPVT14J0y3sW3Up8W2nzU/48QFXfgqldGlK494LEfJlCj tgheNtsnOOmcuM4WtOcla3Oow7oIxAwHUNti53t89obGTmStDL/iI2yKW4NpAua/sy1g Awqz+14Fu7bwVDwfw1Ps6DiAT1GWZ5qVSL3UNKYjUU0n0Q1siDqpRmCTOnnGmQt1w9tu vARg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FQK+F5Tq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m21si3145332otk.132.2019.12.12.07.53.52; Thu, 12 Dec 2019 07:54:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FQK+F5Tq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729603AbfLLPwX (ORCPT + 99 others); Thu, 12 Dec 2019 10:52:23 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:50673 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729416AbfLLPwW (ORCPT ); Thu, 12 Dec 2019 10:52:22 -0500 Received: by mail-wm1-f66.google.com with SMTP id a5so2916697wmb.0 for ; Thu, 12 Dec 2019 07:52:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=ppVt/c6SNGbxwMT06FmYWiQkL8ReCtZAObgQLli/bGc=; b=FQK+F5Tqc8VmatT6qdaJSBwIwwPtF4BX7q+Zo2tSJdUU7H3Poig4l99vIp+I1/Vvlh mimYc8wDLLjPw0140MevtlhicgJTxyOHkfWRR5ay61yk0bxeCWWLe4PrBHC4fIXmy8xg ffcCWN9W2Sts1HHv2X6IJH3dkKfXiIOEIBUem78RJYbraY689kLWgWeWyJNiG3YG7Mru PJyaMuC+g111+wvG/l7UEPS5W5yajVSs2te9dnR4P63kRf/E3jnMGPhIBVqUIGqSyNk7 JlY1+9WWAU6STu+j4Oi234ZDrjlFqABIbb7Sj/1lHOB31K2H9V5kA4HnFDRFrdDawBKB vBHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=ppVt/c6SNGbxwMT06FmYWiQkL8ReCtZAObgQLli/bGc=; b=kwd3rI4OByR0qlEXLe0jc6081E3k/aqJBmbtY70AWatBYDwKQjqUQ2HFuybRYfhCAO qoPj27pjFf469h6TzNEMqanh20IpEiwjjLlSXYK3MTa+wWr630N9tXI7C7cmntJWYWN7 +Oa0aoFH9a5DNNdJn54D2LAibBiSk0C3wQXlh7F4knq0l4vo3qqXYCuuv8WqbLT7L99f 7sUsmdY1cAoudwnYM5GFGB9o1U1FI69T5yH4mls/8R9dUgabeQM2YMK4pUMwpQEF+jUQ bkuSqAnDPX6Wdchj7pnZAMHahptDSKvu/lSJrnLJM9J8TX7judxEu+mFSFzy5qNnJ4Gh rnBg== X-Gm-Message-State: APjAAAVb+EoVNgqHjH43lp5kkwT1jBnFekeUmt24Ek14amsOM18t2Dlz yAeq9Du3e73jLvje9lAYRHcktA== X-Received: by 2002:a1c:14a:: with SMTP id 71mr7609430wmb.48.1576165939689; Thu, 12 Dec 2019 07:52:19 -0800 (PST) Received: from dell ([95.149.164.71]) by smtp.gmail.com with ESMTPSA id z189sm7190746wmc.2.2019.12.12.07.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Dec 2019 07:52:19 -0800 (PST) Date: Thu, 12 Dec 2019 15:52:09 +0000 From: Lee Jones To: Hans de Goede Cc: Maarten Lankhorst , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , "Rafael J . Wysocki" , Len Brown , Andy Shevchenko , linux-acpi@vger.kernel.org, intel-gfx , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] mfd: intel_soc_pmic: Rename pwm_backlight pwm-lookup to pwm_pmic_backlight Message-ID: <20191212155209.GC3468@dell> References: <20191119151818.67531-1-hdegoede@redhat.com> <20191119151818.67531-3-hdegoede@redhat.com> <20191210085111.GQ3468@dell> <20191212084546.GA3468@dell> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 12 Dec 2019, Hans de Goede wrote: > Hi, > > On 12-12-2019 09:45, Lee Jones wrote: > > On Wed, 11 Dec 2019, Hans de Goede wrote: > > > > > Hi Lee, > > > > > > On 10-12-2019 09:51, Lee Jones wrote: > > > > On Tue, 19 Nov 2019, Hans de Goede wrote: > > > > > > > > > At least Bay Trail (BYT) and Cherry Trail (CHT) devices can use 1 of 2 > > > > > different PWM controllers for controlling the LCD's backlight brightness. > > > > > > > > > > Either the one integrated into the PMIC or the one integrated into the > > > > > SoC (the 1st LPSS PWM controller). > > > > > > > > > > So far in the LPSS code on BYT we have skipped registering the LPSS PWM > > > > > controller "pwm_backlight" lookup entry when a Crystal Cove PMIC is > > > > > present, assuming that in this case the PMIC PWM controller will be used. > > > > > > > > > > On CHT we have been relying on only 1 of the 2 PWM controllers being > > > > > enabled in the DSDT at the same time; and always registered the lookup. > > > > > > > > > > So far this has been working, but the correct way to determine which PWM > > > > > controller needs to be used is by checking a bit in the VBT table and > > > > > recently I've learned about 2 different BYT devices: > > > > > Point of View MOBII TAB-P800W > > > > > Acer Switch 10 SW5-012 > > > > > > > > > > Which use a Crystal Cove PMIC, yet the LCD is connected to the SoC/LPSS > > > > > PWM controller (and the VBT correctly indicates this), so here our old > > > > > heuristics fail. > > > > > > > > > > Since only the i915 driver has access to the VBT, this commit renames > > > > > the "pwm_backlight" lookup entries for the Crystal Cove PMIC's PWM > > > > > controller to "pwm_pmic_backlight" so that the i915 driver can do a > > > > > pwm_get() for the right controller depending on the VBT bit, instead of > > > > > the i915 driver relying on a "pwm_backlight" lookup getting registered > > > > > which magically points to the right controller. > > > > > > > > > > Signed-off-by: Hans de Goede > > > > > --- > > > > > drivers/mfd/intel_soc_pmic_core.c | 2 +- > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > For my own reference: > > > > Acked-for-MFD-by: Lee Jones > > > > > > As mentioned in the cover-letter, to avoid breaking bi-sectability > > > as well as to avoid breaking the intel-gfx CI we need to merge this series > > > in one go through one tree. Specifically through the drm-intel tree. > > > Is that ok with you ? > > > > > > If this is ok with you, then you do not have to do anything, I will just push > > > the entire series to drm-intel. drivers/mfd/intel_soc_pmic_core.c > > > does not see much changes so I do not expect this to lead to any conflicts. > > > > It's fine, so long as a minimal immutable pull-request is provided. > > Whether it's pulled or not will depend on a number of factors, but it > > needs to be an option. > > The way the drm subsys works that is not really a readily available > option. The struct definition which this patch changes a single line in > has not been touched since 2015-06-26 so I really doubt we will get a > conflict from this. Always with the exceptions ... OOI, why does this *have* to go through the DRM tree? -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog