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Subject: Re: [PATCH RFC 1/1] genirq: Make threaded handler use irq affinity
 for managed interrupt
To:     Ming Lei <ming.lei@redhat.com>
CC:     "tglx@linutronix.de" <tglx@linutronix.de>,
        "chenxiang (M)" <chenxiang66@hisilicon.com>,
        "bigeasy@linutronix.de" <bigeasy@linutronix.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "maz@kernel.org" <maz@kernel.org>, "hare@suse.com" <hare@suse.com>,
        "hch@lst.de" <hch@lst.de>, "axboe@kernel.dk" <axboe@kernel.dk>,
        "bvanassche@acm.org" <bvanassche@acm.org>,
        "peterz@infradead.org" <peterz@infradead.org>,
        "mingo@redhat.com" <mingo@redhat.com>
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 <20191213171222.GA17267@ming.t460p>
From:   John Garry <john.garry@huawei.com>
Message-ID: <a7ef3810-31af-013a-6d18-ceb6154aa2ef@huawei.com>
Date:   Fri, 13 Dec 2019 17:50:47 +0000
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On 13/12/2019 17:12, Ming Lei wrote:
>> pu list 80-83, effective list 81
>> irq 97, cpu list 84-87, effective list 86
>> irq 98, cpu list 88-91, effective list 89
>> irq 99, cpu list 92-95, effective list 93
>> john@ubuntu:~$
>>
>> I'm now thinking that we should just attempt this intelligent CPU affinity
>> assignment for managed interrupts.
> Right, the rule is simple: distribute effective list among CPUs evenly,
> meantime select the effective CPU from the irq's affinity mask.
> 

Even if we fix that, there is still a potential to have a CPU handling 
multiple nvme completion queues due to many factors, like cpu count, 
probe ordering, other PCI endpoints in the system, etc, so this lockup 
needs to be remedied.

Thanks,
John