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Date:   Thu, 19 Dec 2019 15:33:03 -0800
From:   Tom Anderson <thomasanderson@google.com>
To:     Harry Wentland <harry.wentland@amd.com>,
        Leo Li <sunpeng.li@amd.com>,
        Mikita Lipski <mikita.lipski@amd.com>,
        Alex Deucher <alexander.deucher@amd.com>
Cc:     Christian =?utf-8?B?S8O2bmln?= <christian.koenig@amd.com>,
        David Zhou <David1.Zhou@amd.com>,
        David Airlie <airlied@linux.ie>,
        Daniel Vetter <daniel@ffwll.ch>,
        Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
        Mario Kleiner <mario.kleiner.de@gmail.com>,
        amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] drm/amd/display: Reduce HDMI pixel encoding if max
 clock is exceeded
Message-ID: <20191219233303.GA131109@google.com>
References: <20191202214713.41001-1-thomasanderson@google.com>
 <20191210185924.GA20941@google.com>
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Ping.  Is there any action required to get this landed?

On Tue, Dec 10, 2019 at 10:59:24AM -0800, Tom Anderson wrote:
> Friendly ping.
> 
> On Mon, Dec 02, 2019 at 01:47:13PM -0800, Thomas Anderson wrote:
> > For high-res (8K) or HFR (4K120) displays, using uncompressed pixel
> > formats like YCbCr444 would exceed the bandwidth of HDMI 2.0, so the
> > "interesting" modes would be disabled, leaving only low-res or low
> > framerate modes.
> > 
> > This change lowers the pixel encoding to 4:2:2 or 4:2:0 if the max TMDS
> > clock is exceeded. Verified that 8K30 and 4K120 are now available and
> > working with a Samsung Q900R over an HDMI 2.0b link from a Radeon 5700.
> > 
> > Signed-off-by: Thomas Anderson <thomasanderson@google.com>
> > ---
> >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 45 ++++++++++---------
> >  1 file changed, 23 insertions(+), 22 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 7aac9568d3be..803e59d97411 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -3356,27 +3356,21 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
> >  	return color_space;
> >  }
> >  
> > -static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
> > -{
> > -	if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> > -		return;
> > -
> > -	timing_out->display_color_depth--;
> > -}
> > -
> > -static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
> > -						const struct drm_display_info *info)
> > +static bool adjust_colour_depth_from_display_info(
> > +	struct dc_crtc_timing *timing_out,
> > +	const struct drm_display_info *info)
> >  {
> > +	enum dc_color_depth depth = timing_out->display_color_depth;
> >  	int normalized_clk;
> > -	if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> > -		return;
> >  	do {
> >  		normalized_clk = timing_out->pix_clk_100hz / 10;
> >  		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
> >  		if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> >  			normalized_clk /= 2;
> >  		/* Adjusting pix clock following on HDMI spec based on colour depth */
> > -		switch (timing_out->display_color_depth) {
> > +		switch (depth) {
> > +		case COLOR_DEPTH_888:
> > +			break;
> >  		case COLOR_DEPTH_101010:
> >  			normalized_clk = (normalized_clk * 30) / 24;
> >  			break;
> > @@ -3387,14 +3381,15 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_
> >  			normalized_clk = (normalized_clk * 48) / 24;
> >  			break;
> >  		default:
> > -			return;
> > +			/* The above depths are the only ones valid for HDMI. */
> > +			return false;
> >  		}
> > -		if (normalized_clk <= info->max_tmds_clock)
> > -			return;
> > -		reduce_mode_colour_depth(timing_out);
> > -
> > -	} while (timing_out->display_color_depth > COLOR_DEPTH_888);
> > -
> > +		if (normalized_clk <= info->max_tmds_clock) {
> > +			timing_out->display_color_depth = depth;
> > +			return true;
> > +		}
> > +	} while (--depth > COLOR_DEPTH_666);
> > +	return false;
> >  }
> >  
> >  static void fill_stream_properties_from_drm_display_mode(
> > @@ -3474,8 +3469,14 @@ static void fill_stream_properties_from_drm_display_mode(
> >  
> >  	stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
> >  	stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
> > -	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
> > -		adjust_colour_depth_from_display_info(timing_out, info);
> > +	if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
> > +		if (!adjust_colour_depth_from_display_info(timing_out, info) &&
> > +		    drm_mode_is_420_also(info, mode_in) &&
> > +		    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
> > +			timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
> > +			adjust_colour_depth_from_display_info(timing_out, info);
> > +		}
> > +	}
> >  }
> >  
> >  static void fill_audio_info(struct audio_info *audio_info,
> > -- 
> > 2.24.0.393.g34dc348eaf-goog
> >