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Date:   Fri, 20 Dec 2019 03:07:08 -0800 (PST)
From:   Paul Walmsley <paul.walmsley@sifive.com>
To:     Greentime Hu <greentime.hu@sifive.com>
cc:     green.hu@gmail.com, greentime@kernel.org, hch@lst.de,
        palmer@dabbelt.com, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: fix scratch register clearing in M-mode.
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On Thu, 19 Dec 2019, Greentime Hu wrote:

> This patch fixes that the sscratch register clearing in M-mode. It cleared
> sscratch register in M-mode, but it should clear mscratch register. That will
> cause kernel trap if the CPU core doesn't support S-mode when trying to access
> sscratch.
> 
> Fixes: 9e80635619b5 ("riscv: clear the instruction cache and all registers when booting")
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>

Thanks Greentime, queued for v5.5-rc.

- Paul