Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp3721549ybl; Fri, 20 Dec 2019 14:29:01 -0800 (PST) X-Google-Smtp-Source: APXvYqycTqOJWXIGRZ2/of3qU/Ge9Xgj9LyxmDaVftIyAEBv2azP6MMHFpvTqgeZPFYGNQNRXt4M X-Received: by 2002:a9d:3425:: with SMTP id v34mr16695154otb.142.1576880941121; Fri, 20 Dec 2019 14:29:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1576880941; cv=none; d=google.com; s=arc-20160816; b=lm+/bDkhK5BhltGM/jL00AaMz9E+58WQ16v/6m9KyQfAfCSBxgO/+6gBR02FbHajvA /1pCXu/x1hK2EvFO0w+n7bUcOidKbhLqFjQa3mc4A9lKFX4t3jwF5htHEs2KEFPXISXc sQ9NAGT+f4uhvGkLc21KMrnTMEIbICeCdQce+p0taEvksohDHpDzanQEK+Qy6rnQTJxd 2EFH3FaqwcgD+PJzBldf23oaAnhG+uwFNC8O2hDQltXtZM3sgMvJYx9ijGt1WfkmGIb+ 9AG2IEaMSK6Sy/ENM+l2aktvs0Y9KX8eLkxclc5SF6TfPGQQNBlazXGXxHRloN+2nj7L tYnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=uAY6/g1qyuBMNIyQdm/BfCz69EbNXBXHlTGpzX8helM=; b=Mj+jSyCtLWYfhtntFU4byItpEaK7+7s4F6ksw81bu9AcNW7MCYRhihZ32vq41H1Foc c5KwwjhwwJoRx8+lirvw00zYusAk9338bKgowyySA+mSlbCQt9pmAsT3iH/QM2AqRiPn bs0QbDHKIcAjXj36IpvfnVNlwLSlEqDGi4Gc5lI/fRT2Hl0peowBhrDd7QvT5+U37JWx Zk7QJLYKV32jsWdlPLa8V/oIIu9Q/j9NrLrGIhsNrf8Bsp8F285zxMdAlDlmCZk5Lvvx HZV3MF+4WXJDC5Ud+L5fcPwtC6MG0QKbmDmnRBhiuVM3jvTTxYdZF5SFsgzh/2OPKxhR xYSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=sGzTp1Lc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q66si5258043oig.65.2019.12.20.14.28.36; Fri, 20 Dec 2019 14:29:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=sGzTp1Lc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727706AbfLTW10 (ORCPT + 99 others); Fri, 20 Dec 2019 17:27:26 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:13473 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727688AbfLTW1Z (ORCPT ); Fri, 20 Dec 2019 17:27:25 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 20 Dec 2019 14:27:14 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 20 Dec 2019 14:27:24 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 20 Dec 2019 14:27:24 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 20 Dec 2019 22:27:24 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 20 Dec 2019 22:27:24 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.169.197]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 20 Dec 2019 14:27:23 -0800 From: Sowjanya Komatineni To: , , , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v5 16/19] arm64: tegra: Add clock-cells property to Tegra PMC node Date: Fri, 20 Dec 2019 14:27:02 -0800 Message-ID: <1576880825-15010-17-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576880825-15010-1-git-send-email-skomatineni@nvidia.com> References: <1576880825-15010-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1576880834; bh=uAY6/g1qyuBMNIyQdm/BfCz69EbNXBXHlTGpzX8helM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=sGzTp1LcHgZzEwzLy/oEKS/c3B0/JqchmwxuOyVZJJWe7g4hoyKaAhZnXj76QOsaA flrEGk/u0n4299HtkcqF74hKlx6WESqsRtXMjY1IBWJpGGkG4YfJSWn559VRtLzEOv kExZQHbAojlKdZSWaQy4BpNATgrF6CSvFF2LCCBo5U5f1oEi3snrN6TFSxTAIRvUz8 uQWYJ+PR72vyFmXcpaQRIVu9yzimw2aXnpp/qaA7rT7yNk2UszfcG2aHBfH20Tdx2T jciRhx/EYa09yQl8J2A3U1+nWKB2uH2Mg5b4zk/x4C92LO/YW4Dv7dUC2rQ/xo/jYb rFTxN4jpvPOAw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra132 and Tegra210 PMC block has clk_out_1, clk_out_2, clk_out_3, and a blink clock as a part of PMC. These clocks are moved from clock driver to pmc driver with pmc as a clock provider. Clock ids for these clocks are defined in pmc dt-bindings. This patch updated device tree to include pmc dt-binding and adds #clock-cells property with one clock specifier to pmc node. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 631a7f77c386..79b1e3b01096 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra132", "nvidia,tegra124"; @@ -577,11 +578,12 @@ clock-names = "rtc"; }; - pmc@7000e400 { + tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 48c63256ba7f..3e73b76249f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra210"; @@ -770,16 +771,17 @@ compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&pmc>; + interrupt-parent = <&tegra_pmc>; clocks = <&tegra_car TEGRA210_CLK_RTC>; clock-names = "rtc"; }; - pmc: pmc@7000e400 { + tegra_pmc: pmc@7000e400 { compatible = "nvidia,tegra210-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #clock-cells = <1>; #interrupt-cells = <2>; interrupt-controller; -- 2.7.4