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[209.132.180.67]) by mx.google.com with ESMTP id a64si6651827oif.256.2019.12.21.07.08.01; Sat, 21 Dec 2019 07:08:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=YyXABD20; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727126AbfLUPHM (ORCPT + 99 others); Sat, 21 Dec 2019 10:07:12 -0500 Received: from mail-il1-f194.google.com ([209.85.166.194]:37587 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726802AbfLUPHM (ORCPT ); Sat, 21 Dec 2019 10:07:12 -0500 Received: by mail-il1-f194.google.com with SMTP id t8so10572953iln.4; Sat, 21 Dec 2019 07:07:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=LkyVqaGL8pSvqNm/GP/crRw2qKqaYhVFS2IL3esjjss=; b=YyXABD20DXHsGL/j/uU2X9GW2vWtYA4/REvABc1SKH1P+gDQRaUgyfvrN7RNZLFcCr FE3Ac/vjCvKi0GIE4tdWnfyEliulLr1lEucydp2qpyI7uSmil51FTU+YufrF/ol7cPYy 3jz+O/ZDGl2N1kwK12gqNbDo3O8rHDRgtO5Fe0DrbWNwIkgPjcy/2MowkPNut2ycdeuL eqmZrYwjta8g6lG0nudReRNfMSQDnkAFG2qpH0rAbJh0rZcE6EcqVg6K1jJMoiAj3aN8 a8vlolsXPlaKOLYXNXOiYc3ufw2b1w12tDjhlMw09kGop1Ok33ZFy8Afo/1KDncRMmMH bLlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=LkyVqaGL8pSvqNm/GP/crRw2qKqaYhVFS2IL3esjjss=; b=fA3CYqN1NIuqfdvBWro1nTcZ9r8YB1nRuBk9kXfgp2aL/2Rx0Q9Yzn+yWmtzNgfa+a YOKBOSWAnytiJEZERbK5ABD2rfRoDuEjpcIIp/J+HlOmeGk/kECEg0Glq1Q5NMQav64b WQD9UcpmnLNv1E0IwkMxWpRb5SGFKh2/QTYqoUDNBGuojeUC5rx38xhZF8OrNgnn3YKZ aYn6ktQU7ZbwSwrywmYInqomIOeAbhvJmPeB4rbYZsMFS5iRK0Zc2uN9Sg/5MtJ1Bg60 XEfh5B6kdxto/s1AwHuIenu2szPXolbIEe3eZk0wB8t7mrk+BoJHr141lVpt4tqACFjH teBg== X-Gm-Message-State: APjAAAX+mz2k7vEas0QFGuLPdJaChRwlTAlJSeYxaslVxU+qEcaUnAqy XTvO/KwI6virHS24X5VZEewqvY8VMHRBhkfLqQ3pPA== X-Received: by 2002:a92:1547:: with SMTP id v68mr16711743ilk.58.1576940831051; Sat, 21 Dec 2019 07:07:11 -0800 (PST) MIME-Version: 1.0 References: <20191213160542.15757-1-aford173@gmail.com> In-Reply-To: <20191213160542.15757-1-aford173@gmail.com> From: Adam Ford Date: Sat, 21 Dec 2019 09:06:58 -0600 Message-ID: Subject: Re: [PATCH V2 0/7] soc: imx: Enable additional functionality of i.MX8M Mini To: arm-soc Cc: Peng Fan , Jacky Bai , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree , Linux Kernel Mailing List , Leonard Crestez Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Dec 13, 2019 at 10:05 AM Adam Ford wrote: > > The GPCv2 controller on the i.MX8M Mini is compatible with the driver > used for the i.MX8MQ except for the register locations and names. > The GPCv2 controller is used to enable additional periperals currently > unavailable on the i.MX8M Mini. In order to make them function, > the GPCv2 needs to be adapted so the drivers can associate their > power domain to the GPCv2 to enable them. > > This series makes one include file slightly more generic, > adds the iMX8M Mini entries, updates the bindings, adds them > to the device tree, then associates the new power domain to > both the OTG and PCIe controllers. > > Some peripherals may need additional power domain drivers in the future > due to limitations of the GPC driver, but the drivers for VPU and others are > not available yet. Before I do a V3 to address Rob's comments, I am thinking I'll drop the items on the GPC that Jacky suggested would not work, and we don't have drivers for those other peripherals (GPU, VPU, etc.) anyway. My main goal here was to try and get the USB OTG ports working, so I'd like to enabled enough of the items on the GPC that are similar to the i.MX8MQ and leave the more challenging items until we have either a better driver available and/or actual peripheral support coming. I haven't seen LCDIF or DSI drivers pushed upstream yet, so I doubt we'll see GPU or VPU yet until those are done. Does anyone from the NXP team have any other comments/concerns? adam > > Adam Ford (7): > soc: imx: gpcv2: Rename imx8mq-power.h to imx8m-power.h > soc: imx: gpcv2: Update imx8m-power.h to include iMX8M Mini > soc: imx: gpcv2: add support for i.MX8M Mini SoC > dt-bindings: imx-gpcv2: Update bindings to support i.MX8M Mini > arm64: dts: imx8mm: add GPC power domains > ARM64: dts: imx8mm: Fix clocks and power domain for USB OTG > arm64: dts: imx8mm: Add PCIe support > > .../bindings/power/fsl,imx-gpcv2.txt | 6 +- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 127 ++++++++- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- > drivers/soc/imx/gpcv2.c | 246 +++++++++++++++++- > .../power/{imx8mq-power.h => imx8m-power.h} | 14 + > 5 files changed, 387 insertions(+), 8 deletions(-) > rename include/dt-bindings/power/{imx8mq-power.h => imx8m-power.h} (57%) > > -- > 2.20.1 >