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Tue, 24 Dec 2019 04:10:08 -0600 Received: from [10.24.69.159] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id xBOAA4ei100519; Tue, 24 Dec 2019 04:10:05 -0600 Subject: Re: [PATCH v2 2/3] phy: amlogic: Add Amlogic AXG PCIE PHY Driver To: Remi Pommarel , Yue Wang , Lorenzo Pieralisi , Andrew Murray , Kevin Hilman , Martin Blumenstingl , Neil Armstrong CC: Jerome Brunet , , , References: <20191223214529.20377-1-repk@triplefau.lt> <20191223214529.20377-3-repk@triplefau.lt> From: Kishon Vijay Abraham I Message-ID: <0bf30bee-500c-db91-6647-42ff09e9c8e0@ti.com> Date: Tue, 24 Dec 2019 15:42:01 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20191223214529.20377-3-repk@triplefau.lt> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 24/12/19 3:15 AM, Remi Pommarel wrote: > This adds support for the PCI PHY found in the Amlogic AXG SoC Family. > This will allow to mutualize code in pci-meson.c between AXG and G12A > SoC. > > Signed-off-by: Remi Pommarel > --- > drivers/phy/amlogic/Kconfig | 11 ++ > drivers/phy/amlogic/Makefile | 1 + > drivers/phy/amlogic/phy-meson-axg-pcie.c | 163 +++++++++++++++++++++++ > 3 files changed, 175 insertions(+) > create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c > > diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig > index 1eeb75d018e3..2a3935169ef4 100644 > --- a/drivers/phy/amlogic/Kconfig > +++ b/drivers/phy/amlogic/Kconfig > @@ -60,6 +60,17 @@ config PHY_MESON_G12A_USB3_PCIE > in Meson G12A SoCs. > If unsure, say N. > > +config PHY_MESON_AXG_PCIE > + tristate "Meson AXG PCIE PHY driver" > + default ARCH_MESON > + depends on OF && (ARCH_MESON || COMPILE_TEST) > + select GENERIC_PHY > + select REGMAP_MMIO > + help > + Enable this to support the Meson MIPI + PCIE PHY found > + in Meson AXG SoCs. > + If unsure, say N. > + > config PHY_MESON_AXG_MIPI_PCIE > tristate "Meson AXG MIPI + PCIE PHY driver" > default ARCH_MESON > diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile > index 2167330a0ae8..5fd3a6dca0a5 100644 > --- a/drivers/phy/amlogic/Makefile > +++ b/drivers/phy/amlogic/Makefile > @@ -4,4 +4,5 @@ obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o > obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o > obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o > obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o > +obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o > obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE) += phy-meson-axg-mipi-pcie.o > diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c b/drivers/phy/amlogic/phy-meson-axg-pcie.c > new file mode 100644 > index 000000000000..559c42c1524d > --- /dev/null > +++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c > @@ -0,0 +1,163 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Amlogic AXG PCIE PHY driver > + * > + * Copyright (C) 2019 Remi Pommarel > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define MESON_PCIE_REG0 0x00 > +#define MESON_PCIE_COMMON_CLK BIT(4) > +#define MESON_PCIE_PORT_SEL GENMASK(3, 2) > +#define MESON_PCIE_CLK BIT(1) > +#define MESON_PCIE_POWERDOWN BIT(0) > + > +#define MESON_PCIE_TWO_X1 FIELD_PREP(MESON_PCIE_PORT_SEL, 0x3) > +#define MESON_PCIE_COMMON_REF_CLK FIELD_PREP(MESON_PCIE_COMMON_CLK, 0x1) > +#define MESON_PCIE_PHY_INIT (MESON_PCIE_TWO_X1 | \ > + MESON_PCIE_COMMON_REF_CLK) > +#define MESON_PCIE_RESET_DELAY 500 > + > +struct phy_axg_pcie_priv { > + struct phy *phy; > + struct regmap *regmap; > + struct reset_control *reset; > +}; > + > +static const struct regmap_config phy_axg_pcie_regmap_conf = { > + .reg_bits = 8, > + .val_bits = 32, > + .reg_stride = 4, > + .max_register = MESON_PCIE_REG0, > +}; > + > +static int phy_axg_pcie_power_on(struct phy *phy) > +{ > + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); > + > + regmap_update_bits(priv->regmap, MESON_PCIE_REG0, > + MESON_PCIE_POWERDOWN, 0); > + return 0; > +} > + > +static int phy_axg_pcie_power_off(struct phy *phy) > +{ > + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); > + > + regmap_update_bits(priv->regmap, MESON_PCIE_REG0, > + MESON_PCIE_POWERDOWN, 1); > + return 0; > +} > + > +static int phy_axg_pcie_init(struct phy *phy) > +{ > + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); > + > + regmap_write(priv->regmap, MESON_PCIE_REG0, MESON_PCIE_PHY_INIT); > + return reset_control_reset(priv->reset); > +} > + > +static int phy_axg_pcie_exit(struct phy *phy) > +{ > + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); > + > + return reset_control_reset(priv->reset); > +} > + > +static int phy_axg_pcie_reset(struct phy *phy) > +{ > + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); > + int ret = 0; > + > + ret = reset_control_assert(priv->reset); > + if (ret != 0) > + goto out; > + udelay(MESON_PCIE_RESET_DELAY); > + > + ret = reset_control_deassert(priv->reset); > + if (ret != 0) > + goto out; > + udelay(MESON_PCIE_RESET_DELAY); > + > +out: > + return ret; > +} > + > +static const struct phy_ops phy_axg_pcie_ops = { > + .init = phy_axg_pcie_init, > + .exit = phy_axg_pcie_exit, > + .power_on = phy_axg_pcie_power_on, > + .power_off = phy_axg_pcie_power_off, > + .reset = phy_axg_pcie_reset, > + .owner = THIS_MODULE, > +}; > + > +static int phy_axg_pcie_probe(struct platform_device *pdev) > +{ > + struct phy_provider *pphy; > + struct device *dev = &pdev->dev; > + struct phy_axg_pcie_priv *priv; > + struct device_node *np = dev->of_node; > + struct resource *res; > + void __iomem *base; > + int ret; > + > + priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops); > + if (IS_ERR(priv->phy)) { > + ret = PTR_ERR(priv->phy); > + if (ret != -EPROBE_DEFER) > + dev_err(dev, "failed to create PHY\n"); > + return ret; > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + base = devm_ioremap_resource(dev, res); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + priv->regmap = devm_regmap_init_mmio(dev, base, > + &phy_axg_pcie_regmap_conf); > + if (IS_ERR(priv->regmap)) > + return PTR_ERR(priv->regmap); > + > + priv->reset = devm_reset_control_array_get(dev, false, false); > + if (IS_ERR(priv->reset)) > + return PTR_ERR(priv->reset); > + > + phy_set_drvdata(priv->phy, priv); > + dev_set_drvdata(dev, priv); > + pphy = devm_of_phy_provider_register(dev, of_phy_simple_xlate); > + > + return PTR_ERR_OR_ZERO(pphy); > +} > + > +static const struct of_device_id phy_axg_pcie_of_match[] = { > + { > + .compatible = "amlogic,axg-pcie-phy", dt binding documentation for this too is missing in this series? Thanks Kishon