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From:   Peng Fan <peng.fan@nxp.com>
To:     "srinivas.kandagatla@linaro.org" <srinivas.kandagatla@linaro.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>
CC:     "kernel@pengutronix.de" <kernel@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Peng Fan <peng.fan@nxp.com>
Subject: [PATCH] nvmem: imx: ocotp: introduce ocotp_ctrl_reg
Thread-Topic: [PATCH] nvmem: imx: ocotp: introduce ocotp_ctrl_reg
Thread-Index: AQHVu9YkWVS6MuwrQ0+tW7iZWrxuBQ==
Date:   Thu, 26 Dec 2019 10:20:49 +0000
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From: Peng Fan <peng.fan@nxp.com>

Introduce ocotp_ctrl_reg to include the low 16bits mask of CTRL
register.

i.MX chips will have different layout of the low 16bits of CTRL
register, so use ocotp_ctrl_reg will make it clean to add new
chip support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/nvmem/imx-ocotp.c | 79 ++++++++++++++++++++++++++++++++++---------=
----
 1 file changed, 57 insertions(+), 22 deletions(-)

diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index fc40555ca4cd..4ba9cc8f76df 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -44,6 +44,14 @@
 #define IMX_OCOTP_BM_CTRL_ERROR		0x00000200
 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS	0x00000400
=20
+#define IMX_OCOTP_BM_CTRL_DEFAULT				\
+	{							\
+		.bm_addr =3D IMX_OCOTP_BM_CTRL_ADDR,		\
+		.bm_busy =3D IMX_OCOTP_BM_CTRL_BUSY,		\
+		.bm_error =3D IMX_OCOTP_BM_CTRL_ERROR,		\
+		.bm_rel_shadows =3D IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
+	}
+
 #define TIMING_STROBE_PROG_US		10	/* Min time to blow a fuse */
 #define TIMING_STROBE_READ_NS		37	/* Min time before read */
 #define TIMING_RELAX_NS			17
@@ -62,18 +70,31 @@ struct ocotp_priv {
 	struct nvmem_config *config;
 };
=20
+struct ocotp_ctrl_reg {
+	u32 bm_addr;
+	u32 bm_busy;
+	u32 bm_error;
+	u32 bm_rel_shadows;
+};
+
 struct ocotp_params {
 	unsigned int nregs;
 	unsigned int bank_address_words;
 	void (*set_timing)(struct ocotp_priv *priv);
+	struct ocotp_ctrl_reg ctrl;
 };
=20
-static int imx_ocotp_wait_for_busy(void __iomem *base, u32 flags)
+static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
 {
 	int count;
 	u32 c, mask;
+	u32 bm_ctrl_busy, bm_ctrl_error;
+	void __iomem *base =3D priv->base;
=20
-	mask =3D IMX_OCOTP_BM_CTRL_BUSY | IMX_OCOTP_BM_CTRL_ERROR | flags;
+	bm_ctrl_busy =3D priv->params->ctrl.bm_busy;
+	bm_ctrl_error =3D priv->params->ctrl.bm_error;
+
+	mask =3D bm_ctrl_busy | bm_ctrl_error | flags;
=20
 	for (count =3D 10000; count >=3D 0; count--) {
 		c =3D readl(base + IMX_OCOTP_ADDR_CTRL);
@@ -97,7 +118,7 @@ static int imx_ocotp_wait_for_busy(void __iomem *base, u=
32 flags)
 		 * - A read is performed to from a fuse word which has been read
 		 *   locked.
 		 */
-		if (c & IMX_OCOTP_BM_CTRL_ERROR)
+		if (c & bm_ctrl_error)
 			return -EPERM;
 		return -ETIMEDOUT;
 	}
@@ -105,15 +126,18 @@ static int imx_ocotp_wait_for_busy(void __iomem *base=
, u32 flags)
 	return 0;
 }
=20
-static void imx_ocotp_clr_err_if_set(void __iomem *base)
+static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
 {
-	u32 c;
+	u32 c, bm_ctrl_error;
+	void __iomem *base =3D priv->base;
+
+	bm_ctrl_error =3D priv->params->ctrl.bm_error;
=20
 	c =3D readl(base + IMX_OCOTP_ADDR_CTRL);
-	if (!(c & IMX_OCOTP_BM_CTRL_ERROR))
+	if (!(c & bm_ctrl_error))
 		return;
=20
-	writel(IMX_OCOTP_BM_CTRL_ERROR, base + IMX_OCOTP_ADDR_CTRL_CLR);
+	writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
 }
=20
 static int imx_ocotp_read(void *context, unsigned int offset,
@@ -140,7 +164,7 @@ static int imx_ocotp_read(void *context, unsigned int o=
ffset,
 		return ret;
 	}
=20
-	ret =3D imx_ocotp_wait_for_busy(priv->base, 0);
+	ret =3D imx_ocotp_wait_for_busy(priv, 0);
 	if (ret < 0) {
 		dev_err(priv->dev, "timeout during read setup\n");
 		goto read_end;
@@ -157,7 +181,7 @@ static int imx_ocotp_read(void *context, unsigned int o=
ffset,
 		 * issued
 		 */
 		if (*(buf - 1) =3D=3D IMX_OCOTP_READ_LOCKED_VAL)
-			imx_ocotp_clr_err_if_set(priv->base);
+			imx_ocotp_clr_err_if_set(priv);
 	}
 	ret =3D 0;
=20
@@ -274,7 +298,7 @@ static int imx_ocotp_write(void *context, unsigned int =
offset, void *val,
 	 * write or reload must be completed before a write access can be
 	 * requested.
 	 */
-	ret =3D imx_ocotp_wait_for_busy(priv->base, 0);
+	ret =3D imx_ocotp_wait_for_busy(priv, 0);
 	if (ret < 0) {
 		dev_err(priv->dev, "timeout during timing setup\n");
 		goto write_end;
@@ -306,8 +330,8 @@ static int imx_ocotp_write(void *context, unsigned int =
offset, void *val,
 	}
=20
 	ctrl =3D readl(priv->base + IMX_OCOTP_ADDR_CTRL);
-	ctrl &=3D ~IMX_OCOTP_BM_CTRL_ADDR;
-	ctrl |=3D waddr & IMX_OCOTP_BM_CTRL_ADDR;
+	ctrl &=3D ~priv->params->ctrl.bm_addr;
+	ctrl |=3D waddr & priv->params->ctrl.bm_addr;
 	ctrl |=3D IMX_OCOTP_WR_UNLOCK;
=20
 	writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
@@ -374,11 +398,11 @@ static int imx_ocotp_write(void *context, unsigned in=
t offset, void *val,
 	 * be set. It must be cleared by software before any new write access
 	 * can be issued.
 	 */
-	ret =3D imx_ocotp_wait_for_busy(priv->base, 0);
+	ret =3D imx_ocotp_wait_for_busy(priv, 0);
 	if (ret < 0) {
 		if (ret =3D=3D -EPERM) {
 			dev_err(priv->dev, "failed write to locked region");
-			imx_ocotp_clr_err_if_set(priv->base);
+			imx_ocotp_clr_err_if_set(priv);
 		} else {
 			dev_err(priv->dev, "timeout during data write\n");
 		}
@@ -394,10 +418,10 @@ static int imx_ocotp_write(void *context, unsigned in=
t offset, void *val,
 	udelay(2);
=20
 	/* reload all shadow registers */
-	writel(IMX_OCOTP_BM_CTRL_REL_SHADOWS,
+	writel(priv->params->ctrl.bm_rel_shadows,
 	       priv->base + IMX_OCOTP_ADDR_CTRL_SET);
-	ret =3D imx_ocotp_wait_for_busy(priv->base,
-				      IMX_OCOTP_BM_CTRL_REL_SHADOWS);
+	ret =3D imx_ocotp_wait_for_busy(priv,
+				      priv->params->ctrl.bm_rel_shadows);
 	if (ret < 0) {
 		dev_err(priv->dev, "timeout during shadow register reload\n");
 		goto write_end;
@@ -424,65 +448,76 @@ static const struct ocotp_params imx6q_params =3D {
 	.nregs =3D 128,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx6sl_params =3D {
 	.nregs =3D 64,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx6sll_params =3D {
 	.nregs =3D 128,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx6sx_params =3D {
 	.nregs =3D 128,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx6ul_params =3D {
 	.nregs =3D 128,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx6ull_params =3D {
 	.nregs =3D 64,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx7d_params =3D {
 	.nregs =3D 64,
 	.bank_address_words =3D 4,
 	.set_timing =3D imx_ocotp_set_imx7_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx7ulp_params =3D {
 	.nregs =3D 256,
 	.bank_address_words =3D 0,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx8mq_params =3D {
 	.nregs =3D 256,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx8mm_params =3D {
 	.nregs =3D 256,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct ocotp_params imx8mn_params =3D {
 	.nregs =3D 256,
 	.bank_address_words =3D 0,
 	.set_timing =3D imx_ocotp_set_imx6_timing,
+	.ctrl =3D IMX_OCOTP_BM_CTRL_DEFAULT,
 };
=20
 static const struct of_device_id imx_ocotp_dt_ids[] =3D {
@@ -521,17 +556,17 @@ static int imx_ocotp_probe(struct platform_device *pd=
ev)
 	if (IS_ERR(priv->clk))
 		return PTR_ERR(priv->clk);
=20
-	clk_prepare_enable(priv->clk);
-	imx_ocotp_clr_err_if_set(priv->base);
-	clk_disable_unprepare(priv->clk);
-
 	priv->params =3D of_device_get_match_data(&pdev->dev);
 	imx_ocotp_nvmem_config.size =3D 4 * priv->params->nregs;
 	imx_ocotp_nvmem_config.dev =3D dev;
 	imx_ocotp_nvmem_config.priv =3D priv;
 	priv->config =3D &imx_ocotp_nvmem_config;
-	nvmem =3D devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
=20
+	clk_prepare_enable(priv->clk);
+	imx_ocotp_clr_err_if_set(priv);
+	clk_disable_unprepare(priv->clk);
+
+	nvmem =3D devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
=20
 	return PTR_ERR_OR_ZERO(nvmem);
 }
--=20
2.16.4