Received: by 2002:a25:8b91:0:0:0:0:0 with SMTP id j17csp14057684ybl; Mon, 30 Dec 2019 03:16:19 -0800 (PST) X-Google-Smtp-Source: APXvYqzudULxTN7KEugcnt9wdeOJVeiw/oCvwoMgbknAJGgPqR5Rfh+8BmEKfxa1xVvwehaXhs4g X-Received: by 2002:a9d:7999:: with SMTP id h25mr73800625otm.347.1577704579260; Mon, 30 Dec 2019 03:16:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1577704579; cv=none; d=google.com; s=arc-20160816; b=p4GIMj87ORk+OIpN+xgrROex+rKOcn79HVfyDP+nWwZznghZUidGYaU9jvRHE/fQ8X TxN/Jthw84eOK7vXF+t6rc9nV0tFhF1sO3YnlGXONSgpBQgjyk5PPSBP+W93zxju2xZ/ L53Czrj4RJEnQaLZbX1LmMEDvskbPYs/y9j0DRtdpuVoKiyiARKsdQJyqhmQX4/+esDl qT8Ysxn7kZksE8jv5hvhJaymXFi67JcMnRDzNtbmxhQNKxrXZQJ7D67FL8mFuGwKNt+L yFV5aLR7BTDh7I2JhYuGTksG9+PbgkRfIZFwjrf1mCSjE8yVe/fbtlGyyEX9vevQj2UV bu5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=LOctVp80BX6q2pVKyJ/YJwIyZU/+639El2kXjAMjpEk=; b=YqELiKX1rOg/eBaKHBU+FWyS06ms9jh6nMjxa3qeZ8iKw5f4FpirpOacYDJpxM3hND Heuexl2FhniNjyz+IjOHOarRddKRBut/1P4YlPiQXFdwgkvGqSJifdwDAqdiVapDXvyk gQ/Umwa/nhYCy+CUs5Ke3HojIKKsfb6ZMaNSg8nP3eijZx1Mh9fvBeRe8YlQnSG8xwym q3oXDsUUR+UODszbmE91TTdtmDQxrBUvDrY75JWVawTV9+JF42TXt7YoOMToPMVFHaBT ueTPZYCZnwiUJv1HZZ82wduBxE7wStemXny4792p/LUWle3TJA8QWOfN9ZyD5XqrM6hp 0xXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=BJxpdw7m; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z12si6872905oto.125.2019.12.30.03.16.07; Mon, 30 Dec 2019 03:16:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=BJxpdw7m; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727677AbfL3LOo (ORCPT + 99 others); Mon, 30 Dec 2019 06:14:44 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:15612 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727649AbfL3LOl (ORCPT ); Mon, 30 Dec 2019 06:14:41 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 30 Dec 2019 03:14:01 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Dec 2019 03:14:41 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Dec 2019 03:14:41 -0800 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 30 Dec 2019 11:14:40 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 30 Dec 2019 11:14:40 +0000 Received: from nkristam-ubuntu.nvidia.com (Not Verified[10.19.64.167]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Mon, 30 Dec 2019 03:14:39 -0800 From: Nagarjuna Kristam To: , , , , , , CC: , , , , Nagarjuna Kristam Subject: [Patch V3 17/18] arm64: tegra: Add xudc node for Tegra186 Date: Mon, 30 Dec 2019 16:39:54 +0530 Message-ID: <1577704195-2535-18-git-send-email-nkristam@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1577704195-2535-1-git-send-email-nkristam@nvidia.com> References: <1577704195-2535-1-git-send-email-nkristam@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1577704441; bh=LOctVp80BX6q2pVKyJ/YJwIyZU/+639El2kXjAMjpEk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=BJxpdw7miw2AXSqyNQsCKS39PwwF1FWJ/WxBd9YzMSfrhUA3voGf3p+uxhkTF/GMS 8oYN6yWHt0SZTMnCuV1J9ilo1vtkrByyS4gowiEMItDZHrCecsH5Ioi/sfBNMQMU4w 0UMk1iFvDnvo5QjzI2RDYhjDL5wSwoVs6wIAAf3cs6nAJSlm/oNzELiKpckQ2d4Lfq db+j+JpV0cjZtHk3GztnhzhB7hFxMn/oZ7mMK1GS64b3MUp+HWIqxMiS1vcC0+U3D4 ke3sM04rntsaG9nExsvQxHsoCgzxdBqlnX/NDI5vLZjQqoF/OaFwLSircxLAh5P3VM RjtHAIJEmvnWw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Tegra186 has one XUSB device mode controller, which can be operated HS and SS modes. Add DT entry for XUSB device mode controller. Signed-off-by: Nagarjuna Kristam --- V2-V3: - No changes in this version --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 7893d78..6da9d09 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -554,6 +554,25 @@ #size-cells = <0>; }; + usb@3550000 { + compatible = "nvidia,tegra186-xudc"; + reg = <0x0 0x03550000 0x0 0x8000>, + <0x0 0x03558000 0x0 0x1000>; + reg-names = "base", "fpci"; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_XUSB_CORE_DEV>, + <&bpmp TEGRA186_CLK_XUSB_SS>, + <&bpmp TEGRA186_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA186_CLK_XUSB_FS>; + clock-names = "dev", "ss", "ss_src", "fs_src"; + iommus = <&smmu TEGRA186_SID_XUSB_DEV>; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBB>, + <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; + power-domain-names = "dev", "ss"; + nvidia,xusb-padctl = <&padctl>; + status = "disabled"; + }; + fuse@3820000 { compatible = "nvidia,tegra186-efuse"; reg = <0x0 0x03820000 0x0 0x10000>; -- 2.7.4