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[209.132.180.67]) by mx.google.com with ESMTP id d22si26153487otf.256.2020.01.01.19.38.17; Wed, 01 Jan 2020 19:38:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@brainfault-org.20150623.gappssmtp.com header.s=20150623 header.b=BNzJlPFk; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727592AbgABDh0 (ORCPT + 99 others); Wed, 1 Jan 2020 22:37:26 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:37358 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727525AbgABDh0 (ORCPT ); Wed, 1 Jan 2020 22:37:26 -0500 Received: by mail-wr1-f67.google.com with SMTP id w15so25442382wru.4 for ; Wed, 01 Jan 2020 19:37:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=w0dEwC+ZPQDMRnW2xQ00qFNHx6JYWygNg84CanVuBP4=; b=BNzJlPFkxZL8C3MkzPkV47XFCH4dSlnrY3A8/EowYF+Kw8g8lCGp7wBqI1ZuU/q/kp 9+3UKO8XE9uPErHckqLv3Z3mB80zryYNo0/CYE7VXHcdglhWhM3F5VAjuzjjPZVxUDPE 3QdcItiVds9wegvQHfe4GXJb2D28AnjN86MnF4vUOP3L3hPgbtsOCQkTIB3s89d5+q04 CdNH43gXrUiWgwJG3KtsPpmbt9GPa/T9RphOyotquC/WwgD4pqFOC+od8AdU0wjERts/ zPISwXgmnEqQeBR27T5/b1tMLPqtf9poK9W3KUnnw2wcbSKsybP9mffuIMj2G51pscUI B26Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=w0dEwC+ZPQDMRnW2xQ00qFNHx6JYWygNg84CanVuBP4=; b=lHVxPLREPoJkBPHXlqpRsNqJbqr68xcMjAfLLRUy1eH6ICAA9GXhDPrcWk6u+AOUdd eX+lEFGZRbKwg02oSOU3zGrQptrBqHCoHu9B8GGEQwhkN7jBIVkq2i564ghyslmWdGVk 9TgL2Eb2uMMde7oEDUgMa2vLguNRfiXEstmjqnU8RXom1LX6Qr2gha/rtAAfMQhA28DC /e+tQT4GYlhHKT9t7d96JJuqqrp9wOx6RIDnRHAOTSdhxR2v9adRUFitu/3UUcWV1GJy YYvs40XzFYCcHhNCnahu7DuHGDmy/8HKb9hdlWZIA3KVGfMVySDAl3Ca+GbehhMO5BAT slnw== X-Gm-Message-State: APjAAAWennVb7LaxsOKvRhFjylxm5p4yAfCLg84kG95k5vtqYqZxLBiI YRpuXfycd81+i8nSkNwsR73unYnJ6TOI3InfxduFUyBwink= X-Received: by 2002:adf:fa12:: with SMTP id m18mr76943743wrr.309.1577936244053; Wed, 01 Jan 2020 19:37:24 -0800 (PST) MIME-Version: 1.0 References: <20200102030954.41225-1-zong.li@sifive.com> In-Reply-To: <20200102030954.41225-1-zong.li@sifive.com> From: Anup Patel Date: Thu, 2 Jan 2020 09:07:12 +0530 Message-ID: Subject: Re: [PATCH] riscv: gcov: enable gcov for RISC-V To: Zong Li Cc: corbet@lwn.net, Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-doc@vger.kernel.org, "linux-kernel@vger.kernel.org List" , linux-riscv Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jan 2, 2020 at 8:40 AM Zong Li wrote: > > This patch enables GCOV code coverage measurement on RISC-V. > Lightly tested on QEMU and Hifive Unleashed board, seems to work as > expected. > > Signed-off-by: Zong Li > --- > Documentation/features/debug/gcov-profile-all/arch-support.txt | 2 +- > arch/riscv/Kconfig | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt > index 059d58a549c7..6fb2b0671994 100644 > --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt > +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt > @@ -23,7 +23,7 @@ > | openrisc: | TODO | > | parisc: | TODO | > | powerpc: | ok | > - | riscv: | TODO | > + | riscv: | ok | > | s390: | ok | > | sh: | ok | > | sparc: | TODO | > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index d8efbaa78d67..a31169b02ec0 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -64,6 +64,7 @@ config RISCV > select SPARSEMEM_STATIC if 32BIT > select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU > select HAVE_ARCH_MMAP_RND_BITS if MMU > + select ARCH_HAS_GCOV_PROFILE_ALL > > config ARCH_MMAP_RND_BITS_MIN > default 18 if 64BIT > -- > 2.24.1 > Looks good to me. Reviewed-by: Anup Patel May be (not 100% sure) split this into two patches so that Documentation patch can be taken by Jonathan. Regards, Anup