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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 207sm64170807pfu.88.2020.01.01.23.36.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jan 2020 23:36:10 -0800 (PST) Date: Wed, 1 Jan 2020 23:36:07 -0800 From: Bjorn Andersson To: Brian Masney Cc: agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] firmware: qcom: scm: add 32 bit iommu page table support Message-ID: <20200102073607.GS549437@yoga> References: <20200101033704.32264-1-masneyb@onstation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200101033704.32264-1-masneyb@onstation.org> User-Agent: Mutt/1.12.2 (2019-09-21) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue 31 Dec 19:37 PST 2019, Brian Masney wrote: > Add 32 bit implmentations of the functions > __qcom_scm_iommu_secure_ptbl_size() and > __qcom_scm_iommu_secure_ptbl_init() that are required by the qcom_iommu > driver. > Hi Brian, This looks good, but I was hoping to hoping to reach a conclusion and merge [1] - which in patch 16 squashes the argument filling boiler plate code of the 32 and 64-bit version of scm and hence implements the same. If you have time to take a peek at this series I would greatly appreciate it (not a lot of people testing 32-bit these days...) [1] https://patchwork.kernel.org/project/linux-arm-msm/list/?series=215943 Regards, Bjorn > Signed-off-by: Brian Masney > --- > drivers/firmware/qcom_scm-32.c | 32 ++++++++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c > index 48e2ef794ea3..f149a85d36b0 100644 > --- a/drivers/firmware/qcom_scm-32.c > +++ b/drivers/firmware/qcom_scm-32.c > @@ -638,13 +638,41 @@ int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id, > int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare, > size_t *size) > { > - return -ENODEV; > + int psize[2] = { 0, 0 }; > + int ret; > + > + ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, > + QCOM_SCM_IOMMU_SECURE_PTBL_SIZE, > + &spare, sizeof(spare), &psize, sizeof(psize)); > + if (ret || psize[1]) > + return ret ? ret : -EINVAL; > + > + *size = psize[0]; > + > + return 0; > } > > int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size, > u32 spare) > { > - return -ENODEV; > + struct msm_scm_ptbl_init { > + __le32 paddr; > + __le32 size; > + __le32 spare; > + } req; > + int ret, scm_ret = 0; > + > + req.paddr = addr; > + req.size = size; > + req.spare = spare; > + > + ret = qcom_scm_call(dev, QCOM_SCM_SVC_MP, > + QCOM_SCM_IOMMU_SECURE_PTBL_INIT, > + &req, sizeof(req), &scm_ret, sizeof(scm_ret)); > + if (ret || scm_ret) > + return ret ? ret : -EINVAL; > + > + return 0; > } > > int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, > -- > 2.21.0 >