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Date:   Thu, 2 Jan 2020 16:21:43 +0100
From:   Andrew Lunn <andrew@lunn.ch>
To:     Kai Heng Feng <kai.heng.feng@canonical.com>
Cc:     Heiner Kallweit <hkallweit1@gmail.com>,
        Linux Netdev List <netdev@vger.kernel.org>,
        Kernel development list <linux-kernel@vger.kernel.org>,
        Anthony Wong <anthony.wong@canonical.com>,
        Jason Yen <jason.yen@canonical.com>
Subject: Re: SFP+ support for 8168fp/8117
Message-ID: <20200102152143.GB1397@lunn.ch>
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On Thu, Jan 02, 2020 at 02:59:42PM +0800, Kai Heng Feng wrote:
> Hi Heiner,
> 
> There's an 8168fp/8117 chip has SFP+ port instead of RJ45, the phy device ID matches "Generic FE-GE Realtek PHY" nevertheless.
> The problems is that, since it uses SFP+, both BMCR and BMSR read are always zero, so Realtek phylib never knows if the link is up.
> 
> However, the old method to read through MMIO correctly shows the link is up:
> static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp)
> {
>        return RTL_R8(tp, PHYstatus) & LinkStatus;
> }
> 
> Few ideas here:
> - Add a link state callback for phylib like phylink's phylink_fixed_state_cb(). However there's no guarantee that other parts of this chip works.
> - Add SFP+ support for this chip. However the phy device matches to "Generic FE-GE Realtek PHY" which may complicate things.
> 
> Any advice will be welcome.

Hi Kai

Is the i2c bus accessible? Is there any documentation or example code?

In order to correctly support SFP+ cages, we need access to the i2c
bus to determine what sort of module has been inserted. It would also
be good to have access to LOS, transmitter disable, etc, from the SFP
cage.

   Andrew