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[2001:b011:380f:35a3:d94d:dd84:8131:7958]) by smtp.gmail.com with ESMTPSA id b4sm65574395pfd.18.2020.01.02.08.46.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Jan 2020 08:46:49 -0800 (PST) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 13.0 \(3608.40.2.2.4\)) Subject: Re: SFP+ support for 8168fp/8117 From: Kai-Heng Feng In-Reply-To: <20200102152143.GB1397@lunn.ch> Date: Fri, 3 Jan 2020 00:46:46 +0800 Cc: Heiner Kallweit , Linux Netdev List , Kernel development list , Anthony Wong , Jason Yen Content-Transfer-Encoding: 8BIT Message-Id: References: <2D8F5FFE-3EC3-480B-9D15-23CACE5556DF@canonical.com> <20200102152143.GB1397@lunn.ch> To: Andrew Lunn X-Mailer: Apple Mail (2.3608.40.2.2.4) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Andrew, > On Jan 2, 2020, at 23:21, Andrew Lunn wrote: > > On Thu, Jan 02, 2020 at 02:59:42PM +0800, Kai Heng Feng wrote: >> Hi Heiner, >> >> There's an 8168fp/8117 chip has SFP+ port instead of RJ45, the phy device ID matches "Generic FE-GE Realtek PHY" nevertheless. >> The problems is that, since it uses SFP+, both BMCR and BMSR read are always zero, so Realtek phylib never knows if the link is up. >> >> However, the old method to read through MMIO correctly shows the link is up: >> static unsigned int rtl8169_xmii_link_ok(struct rtl8169_private *tp) >> { >> return RTL_R8(tp, PHYstatus) & LinkStatus; >> } >> >> Few ideas here: >> - Add a link state callback for phylib like phylink's phylink_fixed_state_cb(). However there's no guarantee that other parts of this chip works. >> - Add SFP+ support for this chip. However the phy device matches to "Generic FE-GE Realtek PHY" which may complicate things. >> >> Any advice will be welcome. > > Hi Kai > > Is the i2c bus accessible? I don't think so. It seems to be a regular Realtek 8168 device with generic PCI ID [10ec:8168]. > Is there any documentation or example code? Unfortunately no. > > In order to correctly support SFP+ cages, we need access to the i2c > bus to determine what sort of module has been inserted. It would also > be good to have access to LOS, transmitter disable, etc, from the SFP > cage. Seems like we need Realtek to provide more information to support this chip with SFP+. Kai-Heng > > Andrew