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Date:   Fri, 3 Jan 2020 16:57:21 -0800 (PST)
From:   Paul Walmsley <paul.walmsley@sifive.com>
To:     Yash Shah <yash.shah@sifive.com>
cc:     robh+dt@kernel.org, mark.rutland@arm.com, palmer@dabbelt.com,
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        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
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Subject: Re: [PATCH v2 1/2] riscv: dts: Add DT support for SiFive L2 cache
 controller
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On Fri, 3 Jan 2020, Yash Shah wrote:

> Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file
> 
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

Thanks, queued for v5.5-rc.


- Paul