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References: <20200101033704.32264-1-masneyb@onstation.org> <20200101111521.GA67534@gerhold.net> <CAF6AEGu=G4x3Kpzm=0x-Mj_VOrkvTGq1WcFr8QNAn6APjevHjA@mail.gmail.com>
Cc:     Brian Masney <masneyb@onstation.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Andy Gross <agross@kernel.org>,
        linux-arm-msm <linux-arm-msm@vger.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] firmware: qcom: scm: add 32 bit iommu page table support
To:     Rob Clark <robdclark@gmail.com>,
        Stephan Gerhold <stephan@gerhold.net>
From:   Stephen Boyd <sboyd@kernel.org>
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Date:   Sat, 04 Jan 2020 22:56:59 -0800
Message-Id: <20200105065700.A1292207FD@mail.kernel.org>
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Quoting Rob Clark (2020-01-01 12:14:35)
> On Wed, Jan 1, 2020 at 3:16 AM Stephan Gerhold <stephan@gerhold.net> wrot=
e:
> >
> > On Tue, Dec 31, 2019 at 10:37:04PM -0500, Brian Masney wrote:
> > > Add 32 bit implmentations of the functions
> > > __qcom_scm_iommu_secure_ptbl_size() and
> > > __qcom_scm_iommu_secure_ptbl_init() that are required by the qcom_iom=
mu
> > > driver.
> > >
> > > Signed-off-by: Brian Masney <masneyb@onstation.org>
> > > ---
> > >  drivers/firmware/qcom_scm-32.c | 32 ++++++++++++++++++++++++++++++--
> > >  1 file changed, 30 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_s=
cm-32.c
> > > index 48e2ef794ea3..f149a85d36b0 100644
> > > --- a/drivers/firmware/qcom_scm-32.c
> > > +++ b/drivers/firmware/qcom_scm-32.c
> > > @@ -638,13 +638,41 @@ int __qcom_scm_restore_sec_cfg(struct device *d=
ev, u32 device_id,
> > >  int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
> > >                                     size_t *size)
> > >  {
> > > -     return -ENODEV;
> > > +     int psize[2] =3D { 0, 0 };
> >
> > I would use an explicit size (i.e. __le32) here.
> >
> > > +     int ret;
> > > +
> > > +     ret =3D qcom_scm_call(dev, QCOM_SCM_SVC_MP,
> > > +                         QCOM_SCM_IOMMU_SECURE_PTBL_SIZE,
> > > +                         &spare, sizeof(spare), &psize, sizeof(psize=
));
> > > +     if (ret || psize[1])
> > > +             return ret ? ret : -EINVAL;
> > > +
> > > +     *size =3D psize[0];
> > > +
> > > +     return 0;
> > >  }
> > >
> > >  int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, =
u32 size,
> > >                                     u32 spare)
> > >  {
> > > -     return -ENODEV;
> > > +     struct msm_scm_ptbl_init {
> > > +             __le32 paddr;
> > > +             __le32 size;
> > > +             __le32 spare;
> > > +     } req;
> > > +     int ret, scm_ret =3D 0;
> > > +
> > > +     req.paddr =3D addr;
> > > +     req.size =3D size;
> > > +     req.spare =3D spare;
> >
> > I'm not sure if there is actually anyone using qcom in BE mode (does
> > that even work?), but all the other methods in this file explicitly
> > convert using cpu_to_le32(), so this method should do the same :)
>=20
> sboyd used to occasionally fix things related to qcom in BE back in
> the day.. not sure if modern snapdragons still support BE.
>=20
> (I'm willing to just pretend that they don't.. that lessens the chance
> that someday someone gets far enough to try the GPU in BE mode, and
> realizes they've wasted their time getting that far ;-))
>=20

Yeah it used to work many ages ago, but I don't think anyone besides me
tested it, except maybe for the folks working in QCA back then.