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Sun, 5 Jan 2020 09:05:54 +0000 Received: from oshpigelman2-vm.habana-labs.com (31.154.190.6) by ZR0P278CA0022.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:1c::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2602.11 via Frontend Transport; Sun, 5 Jan 2020 09:05:45 +0000 From: Omer Shpigelman To: "oded.gabbay@gmail.com" CC: "linux-kernel@vger.kernel.org" Subject: [PATCH 2/2] habanalabs: do not halt Coresight during hard reset Thread-Topic: [PATCH 2/2] habanalabs: do not halt Coresight during hard reset Thread-Index: AQHVw6dQ3xASO1vhTkSE0k9uv9gUUQ== Date: Sun, 5 Jan 2020 09:05:45 +0000 Message-ID: <20200105090537.19979-2-oshpigelman@habana.ai> References: <20200105090537.19979-1-oshpigelman@habana.ai> In-Reply-To: <20200105090537.19979-1-oshpigelman@habana.ai> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: ZR0P278CA0022.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:1c::9) To AM0PR02MB5523.eurprd02.prod.outlook.com (2603:10a6:208:15e::24) authentication-results: spf=none (sender IP is ) smtp.mailfrom=oshpigelman@habana.ai; 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Hence avoid halting Coresight during user context close if it is done during hard reset. In addition, we must not reenable clock gating afterwards as it was deliberately disabled in the beginning of the hard reset flow. Signed-off-by: Omer Shpigelman --- drivers/misc/habanalabs/device.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/misc/habanalabs/device.c b/drivers/misc/habanalabs/dev= ice.c index 166883b64725..b680b0caa69b 100644 --- a/drivers/misc/habanalabs/device.c +++ b/drivers/misc/habanalabs/device.c @@ -598,7 +598,9 @@ int hl_device_set_debug_mode(struct hl_device *hdev, bo= ol enable) goto out; } =20 - hdev->asic_funcs->halt_coresight(hdev); + if (!hdev->hard_reset_pending) + hdev->asic_funcs->halt_coresight(hdev); + hdev->in_debug =3D 0; =20 goto out; --=20 2.17.1