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Date:   Sun, 5 Jan 2020 12:31:52 +0100
From:   Sam Ravnborg <sam@ravnborg.org>
To:     Jitao Shi <jitao.shi@mediatek.com>
Cc:     David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
        dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
        srv_heupstream@mediatek.com, yingjoe.chen@mediatek.com,
        eddie.huang@mediatek.com, cawa.cheng@mediatek.com,
        bibby.hsieh@mediatek.com, linux-mediatek@lists.infradead.org,
        ck.hu@mediatek.com, stonea168@163.com
Subject: Re: [PATCH v7 6/8] drm/panel: support for boe,tv101wum-n53 wuxga dsi
 video mode panel
Message-ID: <20200105113152.GB16043@ravnborg.org>
References: <20191012030720.27127-1-jitao.shi@mediatek.com>
 <20191012030720.27127-7-jitao.shi@mediatek.com>
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Hi Jitao.

Looks good.

On Sat, Oct 12, 2019 at 11:07:18AM +0800, Jitao Shi wrote:
> Boe,tv101wum-n53's connector is same as boe,tv101wum-nl6.
> The most codes can be reuse.
> So boe,tv101wum-n53 and boe,tv101wum-nl6 use one driver file.
> Add the different parts in driver data.
> 
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>

> ---
>  .../gpu/drm/panel/panel-boe-tv101wum-nl6.c    | 31 +++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> index e6457f87bc61..7b47619675f5 100644
> --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c
> @@ -624,6 +624,34 @@ static const struct panel_desc auo_kd101n80_45na_desc = {
>  	.discharge_on_disable = true,
>  };
>  
> +static const struct drm_display_mode boe_tv101wum_n53_default_mode = {
> +	.clock = 159833,
> +	.hdisplay = 1200,
> +	.hsync_start = 1200 + 114,
> +	.hsync_end = 1200 + 114 + 10,
> +	.htotal = 1200 + 114 + 10 + 40,
> +	.vdisplay = 1920,
> +	.vsync_start = 1920 + 19,
> +	.vsync_end = 1920 + 19 + 4,
> +	.vtotal = 1920 + 19 + 4 + 10,
> +	.vrefresh = 60,
> +	.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> +};
> +
> +static const struct panel_desc boe_tv101wum_n53_desc = {
> +	.modes = &boe_tv101wum_n53_default_mode,
> +	.bpc = 8,
> +	.size = {
> +		.width_mm = 135,
> +		.height_mm = 216,
> +	},
> +	.lanes = 4,
> +	.format = MIPI_DSI_FMT_RGB888,
> +	.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> +		      MIPI_DSI_MODE_LPM,
> +	.init_cmds = boe_init_cmd,
> +};
> +
>  static int boe_panel_get_modes(struct drm_panel *panel)
>  {
>  	struct boe_panel *boe = to_boe_panel(panel);
> @@ -751,6 +779,9 @@ static const struct of_device_id boe_of_match[] = {
>  	{ .compatible = "auo,kd101n80-45na",
>  	  .data = &auo_kd101n80_45na_desc
>  	},
> +	{ .compatible = "boe,tv101wum-n53",
> +	  .data = &boe_tv101wum_n53_desc
> +	},
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, boe_of_match);
> -- 
> 2.21.0